Researching | Progress and trends of low-jitter fractional-N PLL

Journal of Semiconductors, Volume. 46, Issue 7, 070203(2025)

Progress and trends of low-jitter fractional-N PLL

Jun Yin^1、*, Haoran Li¹, Xiaoqi Lin¹, Rui P. Martins^1,2, and Pui-In Mak¹

Author Affiliations

¹Institute of Microelectronics, University of Macau, Macao, China

²On leave from the Instituto Superior Técnico, Universidade de Lisboa, Lisbon, 1049-001, Portugal

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References(27)

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[19] X Shen, Z Zhang, Y Li et al. A 0.65V-VDD 10.4-to-11.8GHz fractional-N sampling PLL achieving 73.8 fsrms jitter, −271.5dB FoMN, and –61 dBc in-band fractional spur in 40nm CMOS, 338(2025).

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[26] H M Zhang, Y Y Zhu, M Osada et al. A 96fsrms-jitter, –70.6dBc fractional-spur cascaded PLL employing two MMDs with shared DSM for quantization noise cancellation, 1(2025).

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Jun Yin, Haoran Li, Xiaoqi Lin, Rui P. Martins, Pui-In Mak. Progress and trends of low-jitter fractional-N PLL[J]. Journal of Semiconductors, 2025, 46(7): 070203

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Paper Information

Category: Research Articles

Received: Apr. 28, 2025

Accepted: --

Published Online: Aug. 27, 2025

The Author Email: Jun Yin (JYin)

DOI:10.1088/1674-4926/25040035

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