Fractional-N phase-locked loops (PLLs) are widely deployed in high-speed communication systems to generate local oscillator (LO) or clock signals with precise frequency. To support sophisticated modulations for increasing the data rate, the PLL needs to generate low-jitter output^[1]. Since the output frequency of the fractional-N PLL is not an integer multiple of the reference clock frequency (fREF), the phase error seen by the phase detector (PD) contains not only a random part induced by the oscillator and loop noise, but also a deterministic part due to the fractional operation, which is referred to as the quantization error (Q-error). The Q-error has two side effects on the output jitter. Firstly, the Q-error will induce quantization noise in the PLL output. Although the energy of quantization noise can be shaped to high offset frequencies and suppressed by the low-pass characteristics of the loop with the aid of a delta-sigma modulator (DSM), it could still contribute a substantial portion of the output jitter if a moderate or large loop bandwidth is required to suppress the oscillator's phase noise (PN). Secondly, when the Q-error passes through a nonlinear PD, fractional spurs will be generated, and quantization noise at high offset frequencies will be folded into in-band, which also degrades the output jitter. These side effects could limit the jitter performance in fractional-N PLLs. In the following sections, recent techniques to minimize the side effects of Q-error that enable low-jitter fractional-N PLL with high power efficiency will be reviewed.

The classical PLL architecture, utilizing a tri-state phase frequency detector (PFD) and a charge pump (CP), enjoys a wide linear range of the PD, facilitating a robust and fast locking transient. Using an offset PFD-CP^{[2, 3]} to avoid the crossover point of the CP can eliminate the piecewise nonlinearity during phase detection, which suppresses fractional spurs and noise folding induced by the Q-error. The PFD-CP PLL employing an MASH 1-1-1 DSM in Ref. [4] demonstrates a low fractional spur and RMS jitter of −69 dBc and 45.5 fs at a 6.56 GHz output without Q-error compensation. By replacing MASH 1-1-1 with an enhanced nonlinearity-induced-noise-performance (ENOP) DSM, the fractional spur can be further reduced to −79 dBc with only 2.6 fs jitter penalty. However, a small loop bandwidth is required to filter the quantization noise, while a large CP current (56 mA) is needed to lower the in-band phase noise, which calls for large loop filter capacitors. In addition, at a small loop bandwidth, the VCO needs to achieve very low PN in order not to dominate the jitter contribution. Even though the VCO in Ref. [4] is implemented in a 0.18-μm BiCMOS process with a 5-V supply voltage, it still needs to couple four oscillator cores to further reduce the PN, resulting in a large power consumption of 645 mW.

In advanced CMOS technologies with a shrunk supply voltage, it is difficult for the oscillator to achieve a competitive PN as that in Ref. [4]. Therefore, the loop bandwidth has to be increased to suppress the enlarged oscillator PN. To reduce the Q-error, a multipath feedback technology is proposed in Ref. [5], which compensates for the Q-error in the charge domain. As illustrated in Fig. 1(a), this technology first generates two clocks (CK_RETIME0 and CK_RETIME1) with a time space of exactly one oscillator period (TVCO) through a multipath retimer after the multi-modulus divider (MMD). Then, CK_RETIME0 and CK_RETIME1 are selected based on the Q-error information predicted by the DSM to generate multiple feedback clocks. These feedback clocks are compared with the reference clock (CK_REF) through P PFD-CPs with binary-scaled CP currents, which reduces quantization noise power by 22(P−1) times. The fractional spurs and the folded inband noise are limited only by the mismatch among the minimum CP current units. In addition, the offset charge for linearizing the PFD-CP is generated by a voltage source instead of a current source, which reduces the CP noise. In the low-jitter PLL, the oscillator typically dominates the PLL's power consumption. To improve power efficiency, a dual-core VCO based on the inverse-class-F (class-F^-1) topology^[6] and a high-Q circular transformer is proposed, which achieves a high FoM of 194 dBc/Hz at 1 MHz offset. Finally, the PLL in 22-nm CMOS consumes 24.4 mW and measures a fractional spur and RMS jitter of −64.8 dBc and 37.7 fs at a 9.44 GHz output, corresponding to an FoM of − 254.6 dB, which is the highest among recently reported fractional-N PLLs.

Despite achieving a high FoM, the PFD-CP PLL in Ref. [5] still demands a large CP current to suppress the inband PN, necessitating large loop filter capacitors. In addition, the CP relies on long-channel transistors for reducing noise and mismatch also occupies a large area. The area penalty fundamentally comes from the low gain provided by the PFD and CP when converting the phase error to the voltage error^[7], which can only be enlarged by increasing the CP current.

The sampling PDs (SPDs)^[8−10] can provide a high gain to suppress the CP noise. Thus, a small CP current can be used without up-rising the inband PN, resulting in a compact loop filter area. High-gain SPD can be constructed using CK_REF to directly sample the VCO output, which is known as sub-sampling PD (SSPD)^[11]. The sub-sampling PLL is favored by synthesizing a high-frequency output since the frequency dividers are only employed in the frequency-locked loop (FLL) and their noise will not affect the output PN after the PLL is locked. An alternative way to realize a high-gain SPD is to divide the VCO frequency by an MMD to first generate the feedback clock (CK_DIV) first. Then we can use CK_REF to sample CK_DIV^[9] or vice versa^[10].

Since the linear range of the SPD is typically smaller than the Q-error range, the Q-error needs to be compensated for with the help of a digital-to-time converter (DTC)^{[9, 10]} or a digital-to-voltage converter (DAC)^[12]. The DTC or DAC design faces mainly two challenges. Firstly, when the noise contributions from the high-gain PD, CP, and loop filter are minimized, the DTC noise could dominate the inband PN and needs to be reduced. Compared with the DTC, the DAC has a relaxed noise requirement since its noise contribution is also suppressed by the high-gain PD. Secondly, the gain error and non-linearity of the DTC or DAC will induce fractional spurs and noise folding, which must be minimized. The gain mismatch and nonlinearity of the DTC or DAC can be calibrated using a digital adaptive filter, where the tap weights of the adaptive filter are automatically adjusted based on the signed-LMS algorithm^{[10, 12−14]}. In the MMD-based PLL, an effective way to improve the noise and nonlinearity of the DTC is the DTC range reduction technique that uses both the rising and falling edges of the oscillator to re-time the MMD's output^[15]. As a result, the required DTC range is reduced by half. The duty-cycle error of the oscillator output will introduce a deterministic phase error at the input of the PD, which needs to be calibrated by the signed-LMS algorithm and compensated by the DTC. Another direction for DTC noise reduction is to merge the function of the DTC and the high-gain PD, eliminating the threshold comparator in the DTC. The threshold comparator serves to convert the delay information contained in a slow voltage ramp to the time domain and usually dominates the DTC noise. This concept is first demonstrated in Ref. [16] which merges the function of a constant-slope DTC^[17] and SPD.

In Ref. [18], a polarity-reversible SSPD (PR-SSPD) is proposed to apply the DTC range reduction technique to the sub-sampling PLL, as shown in Fig. 1(b). The PR-SSPD keeps the sign of the PD gain always positive, ensuring loop stability when sampling at both the rising and falling edges of the oscillator output. A dual-core source-to-gate transformer-feedback VCO is developed to eliminate the output buffer and maintain low PN. The sub-sampling PLL in 28 nm CMOS consumes 32.2 mW and measures a fractional spur and RMS jitter of −55.2 dBc and 57.9 fs at a 27 GHz output, achieving a best-in-class FoM of −249.7 dB in the millimeter wave (mm-Wave) band. To facilitate extraction of the error signal (e[k]) for calibrating the DTC nonlinearity and the oscillator duty cycle error, the PLL in Ref. [18] uses analog proportional and digital integral paths. Using the digital integral path also eliminates the bulky integration capacitor in the analog loop, resulting in a compact chip area. In Ref. [19], the Q-error of a sampling PLL is compensated for by coarse and fine DTCs, as shown in Fig. 1(c). The function of fine DTC is merged into the SPD through a DAC. A hybrid cascaded digital predistortion is proposed to calibrate the nonlinearity of the coarse DTC, DAC, and SPD, significantly reducing hardware overhead with little noise folding. Circuit techniques are developed to reduce the noise of the DTC and sampling PD at a low supply voltage of 0.65 V. Fabricated in 40 nm CMOS, the sampling PLL demonstrates low fractional spur and RMS jitter of −61 dBc and 73.8 fs at a 10.5 GHz output, achieving a best-in-class FoM of −251.3 dB among low-voltage PLLs.

Bang-bang PD (BBPD) is another type of high-gain PD, widely adopted in digital PLLs^{[13, 20]}. Compared with using a multi-bit time-to-digital converter (TDC), the solution of adopting a BBPD assisted with a DTC exhibits low noise and small nonlinearity while consuming less power. In Ref. [21], the functions of a variable-slope DTC and BBPD are merged to eliminate the threshold comparator, which can reduce the DTC noise, as shown in Fig. 1(d). The digital PLL in 40 nm CMOS demonstrates low fractional spur and RMS jitter of −62.5 dBc and 65 fs at a 10.1 GHz output, achieving a best-in-class FoM of −252.2 dB. The digital loop also helps reduce the loop filter area.

It is worth noting that the above-mentioned high-gain PDs all suffer from a narrow linear range, which could significantly prolong the locking transient. For applications demanding a fast settling time, various techniques developed in Refs. [18, 22−25] can be applied to effectively shorten the locking time. On the other hand, the convergence of the multi-variable DTC nonlinearity calibration using an LMS algorithm is time consuming. Even with the orthogonal polynomial method developed in Ref. [21], the calibration still takes 262 μs to converge at fREF=100 MHz, which can dominate the settling time during the cold start of the PLL.

An alternative direction for Q-error compensation without using a DTC is to cascade two PLLs. In Ref. [26], the Q-error is canceled by changing the phase of the reference clock, which is done using an auxiliary integer-N PLL to generate CK_VCO,aux with a frequency similar to the main fractional-N PLL output (CK_VCO,main), as shown in Fig. 1(e). Two MMDs controlled by the same DSM are utilized to generate the reference and feedback clocks for the main PLL. If the main MMD has a division ratio of N, the quantization noise power can be reduced by ∼N2 times by choosing a division ratio of N+1 or N−1 for the auxiliary MMD. Without using a DTC, the noise contribution and the nonlinearity calibration associated with the DTC are removed. The cascaded PLL in 65 nm CMOS measures a fractional spur and RMS jitter of −70.6 dBc and 95.9 fs at a 5.2 GHz output, corresponding to a FoM of −247.1 dB. The auxiliary PLL including an LC oscillator generates the power and area overhead, which is the cost of avoiding the long convergence time for DTC nonlinearity calibration.

Another approach to exploit the cascaded PLL architecture to realize a DTC-free solution is demonstrated in Ref. [27]. The auxiliary integer-N PLL operates at 7.7 to 9 GHz, which is much lower than the output frequency (25.1 to 28.3 GHz) of the main fractional-N PLL. The main PLL utilizes a harmonic-mixing architecture with a unity feedback gain, which does not amplify the quantization noise and fractional spur induced by the Q-error and nonlinearity from the main PLL loop. Since the sub-10 GHz LC oscillator has a superior PN performance than the mm-Wave oscillator, choosing a small loop bandwidth (fBW,aux) for the auxiliary PLL and a large loop bandwidth fBW,main for the main PLL reduces the output PN at the offset frequencies between fBW,aux and fBW,main. In this cascaded PLL approach, the auxiliary PLL not only aids in eliminating the side effects of the Q-error but also serves to reduce the output jitter. Thus, the cascaded PLL in 7 nm CMOS achieves a high FoM of −250 dB when delivering a 88 fs RMS jitter at 28 GHz output. Nevertheless, the area overhead still exists compared to single-stage PLLs.

In summary, this article reviews recently reported low-jitter fractional-N PLL, revealing the considerations, advantages, and disadvantages of choosing different PLL loop architectures. Neither of the existing PLL architectures can excel in all performance metrics, including jitter, power efficiency, area, and lock/calibration time. The future trends could lie in strengthening the weak points of each architecture. For example, explore the area-reduction techniques for the PFD-CP PLL or investigate novel high-gain PD and DTC/DAC circuits to reduce the number of variables for the nonlinearity calibration or even allow the PLL to be free of the background calibration.