Microelectronics, Volume. 52, Issue 1, 42(2022)

Design of a Controllable Delay Asynchronous FIFO Circuit

CHEN Tingting1,2, LU Feng1,2, WAN Shuqin2, and SHAO Jie2
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
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    References(3)

    [2] [2] CUMMINGS C E. Simulation and synthesis techniques for asynchronous FIFO design [EB/OL]. http://www.sunburst-design.com/papers, 2021-07.

    [7] [7] LIU X, HUI X, LIU H, et al. An efficient blind calibration method for nonlinearity mismatches in M-channel TIADCs [J]. IEICE Elec Expr, 2017, 14(11): 1-11.

    [11] [11] LU H, LIN B, ZHANG S. A digital-background TIADC calibration architecture and a fast calibration algorithm for timing-error mismatch [C] // Int Conf ASIC. Guilin, China. 2007: 253-256.

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    CHEN Tingting, LU Feng, WAN Shuqin, SHAO Jie. Design of a Controllable Delay Asynchronous FIFO Circuit[J]. Microelectronics, 2022, 52(1): 42

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    Paper Information

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    Received: Jul. 24, 2021

    Accepted: --

    Published Online: Jun. 14, 2022

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.210280

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