Microelectronics, Volume. 52, Issue 1, 120(2022)
A Novel Latch-Up-Immune LVTSCR for 5 V Operating Voltage Circuit
[1] [1] VINSON J E, LIOU J J. Electrostatic discharge in semiconductor devices: an overview [J]. IEEE Proceed, 1998, 86(2): 399-420.
[2] [2] KER M D, HSU K C. Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits [J]. IEEE Trans Dev & Mater Reliab, 2005, 5(2): 235-249.
[3] [3] KOO Y, LEE K, KIM K, et al. Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology [J]. Microelec J, 2009, 40(6): 1007-1012.
[4] [4] DUVVURY C, AMERASEKERA A. ESD: a pervasive reliability concern for IC technologies [J]. IEEE Proceed, 1993, 81(5): 690-702.
[5] [5] BLAHO M, POGANY D, GORNIK E, et al. Internal behavior of BCD ESD protection devices under TLP and very-fast TLP stress [J]. IEEE Trans Dev & Mater Reliab, 2004, 4(3): 535-541.
[6] [6] SONG B, HAN Y, LI M L, et al. Substrate-triggered GGNMOS in 65 nm CMOS process for ESD application [J]. Elec Lett, 2010, 46(7): 518-520.
[7] [7] DU F B, SONG S Y, HOU F, et al. An enhanced gate-grounded NMOSFET for robust ESD applications [J]. IEEE Elec Dev Lett, 2019, 40(9): 1491-1494.
[9] [9] LIU Z W, LIOU J J, VINSON J. Novel silicon-controlled rectifier (SCR) for high-voltage electrostatic discharge (ESD) applications [J]. IEEE Elec Dev Lett, 2008, 29(7): 753-755.
[10] [10] CHATTERJEE A, POLGREEN T. A low-voltage triggering SCR for on-chip ESD protection at output and input pads [J]. IEEE Elec Dev Lett, 1991, 12(1): 21-22.
[11] [11] SEMENOV O, SARBISHAEI H, SACHDEV M. Analysis and design of LVTSCR-based EOS/ESD protection circuits for burn-in environment [C] // 6th Int Symp Qual Elec Des. San Jose, CA, USA. 2005: 427-432.
[14] [14] ZHU Z H, YANG Z N, ZHANG Y T, et al. TCAD simulation study of ESD behavior of InGaAs/InP heterojunction tunnel FETs [J]. Crystals, 2020, 10(11): 1059.
[15] [15] LEE J H, LYER N M. Analytical Model ofcorrelation factor for human-body model to transmission-line pulse ESD testing [J]. IEEE Elec Dev Lett, 2017, 38(7): 952-954.
[17] [17] NOTERMANS G, KUPER F, LUCHIES J M. Using an SCR as ESD protection without latch-up danger [J]. Microelec Reliaby, 1997, 37(10-11): 1457-1460.
[18] [18] LIANG H L, XU Q, ZHU L, et al. Design of a gate diode triggered SCR for dual-direction high-voltage ESD protection [J]. IEEE Elec Dev Lett, 2019, 40(2): 163-166.
Get Citation
Copy Citation Text
WANG Songyan, FAN Xiaomei, ZHU Zhihua, ZHANG Yingtao, WANG Yao, LIOU Junjie, CHEN Ruike. A Novel Latch-Up-Immune LVTSCR for 5 V Operating Voltage Circuit[J]. Microelectronics, 2022, 52(1): 120
Category:
Received: Jun. 15, 2021
Accepted: --
Published Online: Jun. 14, 2022
The Author Email: