Journal of Terahertz Science and Electronic Information Technology , Volume. 23, Issue 4, 340(2025)

Design of high-accuracy and megabit True-Time Delay chip

CHEN Yueying, LIU Shuai, YANG Liu, and ZHAO Zirun
Author Affiliations
  • The 13th Research Institute of CETC, Shijiazhuang Hebei 050051, China
  • show less

    Based on the GaAs substrate Enhanced/Depletion-mode pseudomorphic High Electron Mobility Transistor (E/D pHEMT) process, a three-bit adjustable 1 400 ps Digital-Controlled Delay (DCD) chip operating in the 0.5~6 GHz frequency range has been developed. The chip measures 3.60 mm×4.00 mm ×0.07 mm and integrates a three-bit digital-controlled delay line and a 3-bit parallel port drive circuit. Within the 0.5~6 GHz range, the DCD chip exhibits insertion loss of less than 11 dB, with insertion loss variation of less than ±0.5 dB. The Voltage Standing Wave Ratio (VSWR) for both input and output is less than 1.5 across all states. The 1 400 ps delay error can be internally adjusted to ±4 ps, achieving a delay quantity at the nanosecond level. By incorporating additional adjustable units and bonding cut-off methods, the delay accuracy is enhanced to 3‰. The chip features broadband operation, high precision, large delay quantity, and a compact size, making it well-suited for applications in antenna systems.

    Tools

    Get Citation

    Copy Citation Text

    CHEN Yueying, LIU Shuai, YANG Liu, ZHAO Zirun. Design of high-accuracy and megabit True-Time Delay chip[J]. Journal of Terahertz Science and Electronic Information Technology , 2025, 23(4): 340

    Download Citation

    EndNote(RIS)BibTexPlain Text
    Save article for my favorites
    Paper Information

    Category:

    Received: Oct. 26, 2024

    Accepted: May. 29, 2025

    Published Online: May. 29, 2025

    The Author Email:

    DOI:10.11805/tkyda2024573

    Topics