Fig. 1. Diagram of the classical balanced tripler with on-chip MIM capacitor

Fig. 2. Diagram of the proposed and novel 510 GHz tripler structure (a) tripler overall principle structure, (b) 3D view of the bottom part of the waveguide block

Fig. 3. The schematic cross-section and physical image of the fabricated varactors array on 15 μm thick GaAs substrate

Fig. 4. Diagram and simulated result of critical sections of the tripler　Note：(a) input E-plane Y-junction structure with related simulation results, (b) tripler cells in mirror symmetry with matching and filtering networks, (c) output combing structure based on E-probes with related amplitude and phase properties, (d) simulated input coupling per diode

Fig. 5. Final processing structure and physical diagram of the 510 GHz tripler（a）layout of the full monolithic integrated tripler chip with a dimension of 170 μm×1938 μm×15 μm，（b）the circuit mounted on the half split-block，（c）the entire inner close-up view of tripler，（d）dimension and waveguide parameter

Fig. 6. Tolerance analysis of mounting positions and diode parameters　Note: (a) horizontal X offset of installation position, (b) vertical Y offset of installation position, (c) +/- 20% change in DC resistance Rs, (d) +/- 15% change in zero-bias junction capacitor Cj0

Fig. 7. The measured result of 510 GHz tripler (a) test setup for the 490-530 GHz tripler, (b) available 170 GHz doubler output power, (c) the measured output and conversion efficiency as a function of output frequency

Fig. 8. The output power of the tripler at 505 GHz varies with bias voltage，input power

Fig. 9. The spectrum result of the 495 GHz signal produced by tripler（a）the conventional ACST tripler，（b）the proposed tripler