Fig. 1. Traditional digital pixel array circuit renderings^［9］

Fig. 2. Digital pixel array circuit rendering^［9］

Fig. 3. Waveforms of column-line signal（COL）and enable signal for generating 3-bit TH-PWM in the proposed digital pixel driving^［9］

Fig. 4. Simplified pixel array schematic and timing diagram of the proposed data addressing technique with DRD method^［12］

Fig. 5. Pixel array schematics and timing diagrams of data and scan signals for displaying test pattern using proposed technique^［12］

Fig. 6. Block diagram of test board^［11］

Fig. 7. Cross-sectional views of coplanar a-IGZO with（a）conventional TFT and（b）the proposed TFT^［15］

Fig. 8. （a）Photographs and（b）measured transfer curves of the proposed TFTs and conventional TFTs^［15］

Fig. 9. （a）Circuit schematic and（b）timing diagram of one stage of the scan driver^［15］

Fig. 10. Output voltage of scan driver with（a）conventional and（b）low power scanning driver^［15］

Fig. 11. Schematic diagram of conventional driving and proposed selective scan driving^［22］

Fig. 12. （a）Circuit diagram and（b）timing diagram proposed in Ref.［22］

Fig. 13. Detailed operation of proposed scan driver circuit^［22］

Fig. 14. I/O interface and the symbol of the proposed pseudo multi-port memory circuit for the 3×3 filter application^［29］

Fig. 15. Complete block diagram of the proposed pseudo multi-port memory circuit^［28］

Fig. 16. Address decoding circuit of the proposed pseudo multi-port memory circuit^［28］

Fig. 17. Block diagram of TFT-LCD system^［36］

Fig. 18. Schematics of ramp wave circuit^［36］

Fig. 19. Block diagram of new fully digital driving method^［36］

Fig. 20. Block diagrams for one data driving channel in conventional and new fully digital driving circuits^［36］