In order to enhance the quality of image display and reduce the consumption of hardware resources in the bilateral filtering algorithm based on field programmable logic devices (FPGAs), a piecewise approximation bilateral filtering algorithm is designed. The piecewise approximation reduces the storage capacity of the range domain and the bit width of the output data in bilateral filtering, thus reducing the computational complexity and hardware resource consumption. The bilateral filtering algorithm of piecewise approximation is implemented on the FPGA platform of Zynq-7000 and Sparten-7, and the performance of filtering and edge preserving under different Gaussian noise and its optimal range standard deviation is studied. The results show that the performance is comparable to that of the traditional bilateral filtering algorithm, the use of look-up table (LUT) and digital signal processing module (DSP) is reduced by 9.9% and 71.1% compared to the conventional bilateral filtering algorithm, and the power consumption is only 0.128 W. The algorithm is suitable for image filtering application scenarios with limited hardware resources.