[1] [1] BUCHER M,NIKOLAOU A, PAPADOPOULOU A, et al. Total ionizing dose effects on analog performance of 65 nm bulk CMOS with enclosed-gate and standard layout ［C］ // IEEE ICMTS. Austin, TX, USA. 2018: 166-170.

[2] [2] GIRALDOA, PACCAGNELLA A, MINZONI A. Aspect ratio calculation in N-channel MOSFETs with a gate-enclosed layout ［J］. Sol Sta Elec, 2000, 44(6): 981-989.

[3] [3] VAZ P I, BOTH T H, VIDOR F F, et al. Design flow methodology for radiation hardened by design CMOS enclosed-layout-transistor-based standard-cell library ［J］. J Elec Test, 2018, 34: 735-747.

[4] [4] FAN X,LI P, LI W, et al. Gate-enclosed NMOS transistors ［J］. J Semicond, 2011, 32(8): 0804022.

[5] [5] SNOEYS W J, GUTIERREZ T A P, ANELLI G. A new NMOS layout structure for radiation tolerance ［J］.IEEE Trans Nucl Sci, 2002, 49(4): 1829-1833.

[9] [9] FLEETWOOD D M. Evolution of total ionizing dose effects in MOS devices with Moore’s law scaling ［J］. IEEE Trans Nucl Sci, 2018, 65(8): 1465-1481.