Fig. 1. “Electronic control-electronic computing-photonic interconnect” paradigm: optical interconnection. (a) Bandwidth growth trend at chip interfaces; (b) CPO schematic; (c) OIO schematic

Fig. 2. “Electronic control-electronic computing-photonic interconnect” paradigm: optical routing. (a) Thermo-optical switches in 32×32 Benes topology^[25]; (b) structure schematic of 32×32 switch architecture with multi-layer on Si₃N₄-on-SOI platform^[27]; (c) 128×128 electro-optical switch^[31]; (d) 240×240 MEMS Cross-Bar silicon-based large-scale array optical switch^[33]; (e) silicon photonic MEMS switches based on SWX^[34]

Fig. 3. “Electronic control-photonic computing-photonic interconnect” paradigm: functional units. (a) MZI-based photonic linear accelerator^[38]; (b) Fourier transform-based accelerator^[40]; (c) on-chip silicon diffraction linear processor using 1D dielectric metasurfaces^[41]; (d) nonlinear unit implementations for photonic computing

Fig. 4. “Electronic control-photonic computing-photonic interconnect” paradigm: PNN. (a) Optical distributed computing architecture integrating diffraction/interference^[54]; (b) 3 layers cascaded optical fully connected neural network chip^[55]; (c) wavelength- encoded asynchronous optical computing Ising machine^[56]; (d) Lightmatter photonic accelerator ^[57]; (e) Lightelligence photonic accelerator^[35]

Fig. 5. Energy efficiency advantage and high-performance unit devices. (a) Energy efficiency scaling with photonic chip size; (b) device performance constraints on system scaling; (c) high performance device library: low random phase error and low-loss passive devices, high-speed and efficient active devices^[65-70]