Driven by emerging technologies such as artificial intelligence, the explosive growth in computing power demands, coupled with the constraints of advanced electronic chip fabrication processes, has positioned silicon-based photoelectronic synergistic integration as a critical pathway to overcome the bandwidth, latency, and energy efficiency bottlenecks inherent in the traditional “electronic control-electronic computing-electronic interconnect (EEE)” paradigm. Currently, two evolutionary paradigms dominate photoelectronic synergistic technology, namely “electronic control-electronic computing-photonic interconnect (EEP)” and “electronic control-photonic computing-photonic interconnect (EPP)”. The former focuses on leveraging the high-speed advantages of photonic interconnects to enhance data transfer efficiency between and within chips, while the latter further exploits the potential of photonic computing to accelerate computation-intensive tasks in neural networks.

This review systematically summarizes the current status and trends in silicon-based photoelectronic synergistic integration, highlighting key technologies and representative achievements within the EEP and EPP paradigms. For EEP, we survey optical I/O (OIO) architectures enabling terabit chip-to-chip links; innovations in co-packaged optics (CPO) and linear-drive pluggable optics (LPO) reducing latency and energy; and large-scale optical switches such as 128×128 electro-optic arrays with sub-2-ns switching. For EPP, progress spans photonic linear accelerators using Mach-Zehnder interferometer (MZI) networks, diffraction structures, and wavelength-division multiplexing; electro-optic nonlinear units such as graphene/silicon heterojunctions for activation functions; and integrated photonic neural networks achieving breakthroughs such as 160-TOPS/W (TOPS: tera operations per second) efficiency. Crucially, scaling such systems hinges on high-performance elementary devices: ultra-low-loss passive components (waveguide crossings, delay lines) and high-efficiency active devices (modulators, detectors).

Silicon-based photoelectronic synergistic integration offers transformative efficiency and parallelism but faces distinct challenges: EEP technologies (CPO/LPO modules, OIO chiplets) approach commercialization to address imminent interconnect bottlenecks, while EPP solutions (photonic tensor cores) remain laboratory demonstrations requiring breakthroughs in scalable nonlinearity and algorithm-hardware co-design. This difference in commercialization phases establishes a symbiotic relationship: mature optical interconnect technologies (EEP) will provide the essential infrastructure platform for deploying optical computing systems (EPP), collectively forming a heterogeneous ecosystem for next-generation high-performance computing. Silicon-based photoelectronic synergistic integration will progress through three key thrusts: heterogeneous integration of electronic and photonic components; architectural innovations enabling dynamic computing-communication convergence; and application-tailored co-design of photonic computing hardware with optimized algorithms. Currently in its rapid development phase, this field represents a catalytic force in computational architecture, where the synergistic interplay of photonic and electronic technologies will propel artificial intelligence and high-performance computing into a new developmental era.