Low temperature complementary metal oxide semiconductor (CMOS) or cryogenic CMOS is a promising avenue for the continuation of Moore's law while serving the needs of high performance computing. With temperature as a control “knob” to steepen the subthreshold slope behavior of CMOS devices, the supply voltage of operation can be reduced with no impact on operating speed. With the optimal threshold voltage engineering, the device ON current can be further enhanced, translating to higher performance. In this article, the experimentally calibrated data was adopted to tune the threshold voltage and investigated the power performance area of cryogenic CMOS at device, circuit and system level. We also presented results from measurement and analysis of functional memory chips fabricated in 28 nm bulk CMOS and 22 nm fully depleted silicon on insulator (FDSOI) operating at cryogenic temperature. Finally, the challenges and opportunities in the further development and deployment of such systems were discussed.