Fig. 1. Linear optimization method design flow diagram（HB：Harmonic Balance）

Fig. 2. Optimal input and output embedding impedances for the diode

Fig. 3. Schematic of the waveguide cavity where the diode cell is suspended

Fig. 4. Schematic for optimization of the input matching network circuit

Fig. 5. Design of input matching network：（a）detailed dimensions of the input matching network；（b）comparison of PortZ₀ and Epsilon for suspended and non-suspended microstrip lines with a width of 100 µm for the TE₁₀ mode；（c）comparison of the diode's input embedding impedance with the impedance provided by the input matching network

Fig. 6. Schematic for optimization of the output matching network circuit

Fig. 7. Design of the output matching network：（a）detailed dimensions of the output waveguide matching；（b）the detail of the 340 GHz frequency doubler chip；（c）comparison of the diode's output embedding impedance with the impedance provided by the output matching network

Fig. 8. Assembled frequency doubler

Fig. 9. Diagram of the frequency doubler test setup

Fig. 10. Test results of the 340 GHz doubler：（a）measured input power and output power versus frequencies；（b）comparison of measured efficiency and simulated efficiency with different series resistances（simulated input power P_in=150 mW）

Fig. 11. The effect of assembly errors on output：（a）schematic of the lateral assembly error；（b）impact of different offset values on the output efficiency，with R_s•C_j0 = 120 Ω•fF and P_in=150 mW

Fig. 12. Defects on the surface of the output waveguide