Fig. 1. Schematic and 3-D model of the 110 and 220 GHz balanced triplers：（a）Schematic of the balanced triplers；（b）3-D model of 110 GHz tripler；（c）3-D model of 220 GHz tripler

Fig. 2. 3-D model of integrated on-chip capacitance：（a）Top view of integrated on-chip capacitor and surrounding circuits；（b）Enlarged side view of integrated on-chip capacitor

Fig. 3. 3-D model of integrated on-chip capacitance：（a）Top view of integrated on-chip capacitor and surrounding circuits；（b）Enlarged side view of integrated on-chip capacitor

Fig. 4. Configuration of proposed band stop filter in tripler

Fig. 5. Simulated results of the band stop filter and stepped impedance LPF：（a）Simulated results for 110 GHz tripler；（b）Simulated results for 220 GHz tripler

Fig. 6. Test module of 110 GHz tripler and details of the circuits：（a）The split-block of 110 GHz tripler；（b）Enlarged view of surrounding circuits and the chip in tripler；（c）Enlarged view of the details on diodes

Fig. 7. Test platform of 110/220 GHz tripler

Fig. 8. Measured results of 110 GHz tripler

Fig. 9. Test module of 220 GHz tripler and details of the circuits：（a）The split-block of 220 GHz tripler；（b）Enlarged view of surrounding circuits and the chip in tripler；（c）Enlarged view of single path

Fig. 10. Measured and simulated results of 220 GHz tripler