Microelectronics, Volume. 55, Issue 1, 109(2025)

A Low-power High-precision Oversampling SAR ADC Circuit

XU Ning, JIANG Fuling, ZHAO Junjie, ZHONG Guoqiang, LIU Zhao, JIANG Qian, XIONG Botao, SHEN Rensheng, and CHANG Yuchun
Author Affiliations
  • School of Integrated Circuits, Dalian University of Technology, DaLian, Liaoning 116000, P R China
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    References(11)

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    [3] [3] BAGHERI M, SCHEMBARI F, POURMOUSAVIAN N, et al. A mismatch calibration technique for sar adcs based on deterministic self-calibration and stochastic quantization[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2020, 67(9): 2883-2896.

    [4] [4] TSENG W H, LEE W L, HUANG C Y, et al. A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for digitally-assisted wireless transmitters[J]. IEEE Journal of Solid-State Circuits, 2016, 51(10): 2222-2231.

    [5] [5] KATOH R, KOBAYASHI S, WAHO T. A dynamic element matching circuit for multi-bit delta-sigma modulators[C]//ASP-DAC. Yohohama, Japan.2004: 569-570.

    [6] [6] SHU Y S, KUO L T, LO T Y. An oversampling SAR ADC with DAC mismatch error shaping achieving 105 dB SFDR and 101 dB SNDR over 1 kHz BW in 55 nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2016, 51(12): 2928-2940.

    [7] [7] JIE L, TANG X, LIU J, et al. An overview of noise-shaping SAR ADC: from fundamentals to the frontier[J]. IEEE Open Journal of the Solid-State Circuits Society, 2021, 1(3): 149-161.

    [8] [8] FREDENBURG J, FLYNN M. A 90 MS/s 11 MHz bandwidth 62 dB SNDR noise-shaping SAR ADC[C]//IEEE ISSCC. San Francisco, CA, USA. 2012: 468-470.

    [9] [9] YANG C, QIU L, TANG K, et al. A 98.6 dB SNDR SAR ADC with a mismatch error shaping technique implemented with double sampling[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2022, 69(3): 774-778.

    [10] [10] VAN ELZAKKER M, VAN TUIJL E, GERAEDTS P, et al. A 1.9 W 4.4fJ/Conversion-step 10 b 1 MS/s Charge-Redistribution ADC[C]//IEEE ISSCC. Francisco, CA, USA. 2008: 244-610.

    [11] [11] LI H, SHEN Y, XIN H, et al. A 7.3- W 13-ENOB 98-dB SFDR noise-shaping SAR ADC with duty-cycled amplifier and mismatch error shaping[J]. IEEE Journal of Solid-State Circuits, 2022, 57(7): 2078-2089.

    [12] [12] SHEN Y, LI H, XIN H, et al. A 103-dB SFDR calibration-free oversampled sar adc with mismatch error shaping and pre-comparison techniques[J]. IEEE Journal of Solid-State Circuits, 2022, 57(3): 734-744.

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    XU Ning, JIANG Fuling, ZHAO Junjie, ZHONG Guoqiang, LIU Zhao, JIANG Qian, XIONG Botao, SHEN Rensheng, CHANG Yuchun. A Low-power High-precision Oversampling SAR ADC Circuit[J]. Microelectronics, 2025, 55(1): 109

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    Paper Information

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    Received: Feb. 7, 2024

    Accepted: Jun. 19, 2025

    Published Online: Jun. 19, 2025

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.240031

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