[1] [1] WALLASH A. ESD challenges in magnetic recording: Past, present and future[C]//IEEE International Reliability Physics Symposium Proceedings, 2003.41st Annual. Dallas, TX, USA. 2003: 222-228.

[2] [2] LIANG H L, GU X F, DONG S R, et al. RC-embedded LDMOS-SCR with high holding current for high-voltage I/O ESD protection[J]. IEEE Transactions on Device and Materials Reliability, 2015, 15(4): 495-499.

[3] [3] SHAN Y, HE J, HU B, et al. NLDD/PHALO-assisted low-trigger SCR for high-voltage-tolerant ESD protection without using extra masks[J]. IEEE Electron Device Letters, 2009, 30(7): 778-780.

[5] [5] LIN C Y, WU Y H, KER M D. Low-leakage and low-trigger-voltage SCR device for ESD protection in 28-nm high-kmetal gate CMOS process[J]. IEEE Electron Device Letters, 2016, 37(11): 1387-1390.

[6] [6] AMERASEKERA A, DUVVURY C. The impact of technology scaling on ESD robustness and protection circuit design[J]. IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part A, 1995, 18(2): 314-320.

[7] [7] WANG A Z H, TSAY C H. On a dual-polarity on-chip electrostatic discharge protection structure[J]. IEEE Transactions on Electron Devices, 2001, 48(5): 978-984.

[8] [8] DUVVURY C. ESD qualification changes for 45nm and beyond[C]//IEEE International Electron Devices Meeting. San Francisco, CA, USA. 2008: 1-4.

[9] [9] QI Z, QIAO M, ZHAO F, et al. Novel integrated low capacitance transient voltage suppressor array with capacitance equalization technique for system-level EOS/ESD protection[C]//33rd International Symposium on Power Semiconductor Devices and ICs. Nagoya, Japan. 2021: 203-206.

[10] [10] SHRIER K, TRUONG T, FELPS J. Transmission line pulse test methods, test techniques and characterization of low capacitance voltage suppression device for system level electrostatic discharge compliance[C]//Electrical Overstress/Electrostatic Discharge Symposium. Grapevine, TX, USA. 2004: 1-10.

[11] [11] DONG S R, JIN H, MIAO M, et al. Novel capacitance coupling complementary dual-direction SCR for high-voltage ESD[J]. IEEE Electron Device Letters, 2012, 33(5): 640-642.