Fig. 1. Infrared dynamic vision sensor chip structure diagram

Fig. 2. AER logical structure

Fig. 3. Cascading of two input arbitration units

Fig. 4. Round-robin arbiter workflow

Fig. 5. Row information compression

Fig. 6. Example of row data compression

Fig. 7. Ping-pong operation of RAM

Fig. 8. Ping-pong operation sequence diagram of RAM

Fig. 9. Verification results of the FPGA of the digital processing module of the DVS chip

Fig. 10. Verification results of DVS chip visualization method