Fig. 1. (Color online) Fabricated 200 mm GaN-on-SOI wafer with CMOS-compatible processing.

Fig. 2. (Color online) (a) Schematic cross-section of the epitaxial layer stack and (b) processing flow.

Fig. 3. (Color online) (a) Microscope images, (b) transfer characteristics, and (c) OFF-state leakage characteristics of the logic HEMTs with L_GD of 1.5 μm and W_G scaling from 6 μm to 2 μm.

Fig. 4. (Color online) (a) Microscope image, (b) schematic, and (c) measured voltage transfer characteristic (VTC) of the integrated RTL inverter.

Fig. 5. (Color online) (a) Comparator designed by RTL and (b) the microscope image of the processed comparator.

Fig. 6. (Color online) (a) Voltage transfer characteristics of the comparator with (a) various V_DD and (b) various reference voltage V_REF.

Fig. 7. (Color online) (a) Undervoltage lockout GaN circuit, (b) layout, and (c) voltage transfer characteristics show the IC shuts down when V_DD < 5 V and restarts when V_DD > 5.7 V.