Fig. 1. Conventional digital pixel with SS-ADC

Fig. 2. Block diagram of the proposed DROIC with the novel pixel-level SS-ADC

Fig. 3. Timing diagram of the proposed DROIC

Fig. 4. （a）The circuit diagram，and（b）the timing diagram of proposed power-self-adaptive pulse comparator：（a）（b）

Fig. 5. Simulation results of IC when VINT equals (a) 0.8V, (b) 1.5 V, respectively

Fig. 6. The circuit diagram of the pixel dynamic memory and the column data W/R circuit

Fig. 7. （a）The microphotograph of the DROIC，（b）custom-designed PCB to test the DROIC

Fig. 8. the layout of 2×2 pixels

Fig. 9. Measured VRAMP captured by oscilloscope

Fig. 10. SNR histogram of the whole pixel array at the full well

Fig. 11. When VRST=1.35V（a）the gray-scale image of the DROIC，（b）the gray-scale image of FPN

Fig. 12. The digital output versus the reset voltage VRST

Fig. 13. The non-linearity versus the reset voltage VRST