Fig. 1. Diagram of the classical balanced tripler relying on on-chip MIM capacitor

Fig. 2. (a) Diagram of the face-to-face balanced tripler architecture, (b) 3D-view of the proposed configuration

Fig. 3. (a) E-plane Y-junction waveguide power splitter and its amplitude and phase properties, (b) diagram of the E-plane waveguide-to-microstrip transition structure pair

Fig. 4. Suspended matching and filtering networks including diode pairs in mirror symmetry

Fig. 5. E-plane probe-based differential combining structure with related performances

Fig. 6. Photograph of the fabricated balanced tripler module and its details

Fig. 7. Measurement platform of the balanced tripler module

Fig. 8. (a) Driven power of the proposed tripler module, (b) measured performances of the fabricated balanced tripler module

Fig. 9. Comparisons of the simulated and measured output power of the balanced tripler module