AEROSPACE SHANGHAI, Volume. 42, Issue 3, 104(2025)
Design and Testing Verification of a High-capacity Spaceborne Storage Module Based on VPX Architecture for High-Speed Access
Figures & Tables(15)
Fig. 3. Schematic diagram of the backboard interconnection relationship
Fig. 6. Composition block diagram of the testing verification environment
Fig. 8. Operation interfaces of the test board and accompanying test board
Table 1.
Adaptation frequencies of the FPGA crystal oscillator View tableView in ArticleTable 1.
Adaptation frequencies of the FPGA crystal oscillator 协议 速度 2.500 Gbit/s 3.125 Gbit/s 5.000 Gbit/s 6.250 Gbit/s GTX 125 MHz/200 MHz 125 MHz/200 MHz 125 MHz/200 MHz 125 MHz AURORA_8b10b 125 MHz/200 MHz 125 MHz/200 MHz 125 MHz/200 MHz 125 MHz AURORA_64b66b 125 MHz/200 MHz 125 MHz/200 MHz 125 MHz/200 MHz 125 MHz SRIO 125 MHz 125 MHz 125 MHz 156.25 MHz
Table 2.
Statistics of the design margin for the module power supply View tableView in ArticleTable 2.
Statistics of the design margin for the module power supply 电源 需求电流/A 设计电流/A 使用率/% 裕度/% VCC0.9 38.90 50 75.44 24.56 VCC1.0 32.90 50 66.80 33.20 VCC1.2 4.60 13 75.00 25.00 VCC1.5 9.50 13 25.56 74.44 VCC1.8 4.13 8 69.50 29.50 VCC2.0 0.47 2 10.25 89.75 VCC2.5 0.76 2 33.25 66.75 VCC3.3 1.85 4 42.42 57.58
Table 3.
Requirements of the power-up sequence of the main chips on the storage module View tableView in ArticleTable 3.
Requirements of the power-up sequence of the main chips on the storage module 序号 芯片名称 时序要求 1 JFM7VX690T80 1.0->1.8->1.5；1.0->MGTAVCC1.0->MGTAVTT1.2或MGTAVCC1.0->1.0->MGTAVTT1.2 2 HI3559A 0.90->1.00->3.30->2.50->1.80->1.35
Table 4.
Definitions of the connectors on the TTE daughter cards View tableView in ArticleTable 4.
Definitions of the connectors on the TTE daughter cards 序号 A B C D 1 PCIeR0+ PCIeR0- SMA_DATA+ SMA_DATA- 2 GND GND GND GND 3 PCIeR3+ PCIeR3- NC NC 4 GND GND GND GND 5 PCIeR2+ PCIeR2- GTP1_RX+ GTP1_RX- 6 GND GND GND GND 7 PCIeR1+ PCIeR1- NC NC 8 GND GND GND GND 9 NC NC NC NC 10 GND GND GND GND 11 PCIeT0+ PCIeT0- GTP0_RX+ GTP0_RX- 12 GND GND GND GND 13 PCIeT2+ PCIeT2- GTP0_TX+ GTP0_TX- 14 GND GND GND GND 15 PCIeT1+ PCIeT1- GTP1_TX+ GTP1_TX- 16 GND GND GND GND 17 PCIeT3+ PCIeT3- NC PCIe_RST# 18 GND GND GND GND 19 PCIeCLK+ PCIeCLK- NC NC 20 5V_IN 5V_IN 5V_IN 5V_IN
Table 5.
Performance indicators of the time-triggered Ethernet View tableView in ArticleTable 5.
Performance indicators of the time-triggered Ethernet 序号 指标 技术指标要求 1 通信速率 网络速率单路支持最高1 Gbit/s 2 消息 依据调度表实现TT、RC、BE业务混合发送 3 时钟同步精度 小于1 μs 4 端口冗余 具备双端口冗余发送与接收冗余管理
Table 6.
Commands of tests for the storage module file management capabilities View tableView in ArticleTable 6.
Commands of tests for the storage module file management capabilities 序号 命令 运行 运行正常依据 测试功能 1 cd /mnt 进入挂载目录 输入pwd命令查看当前位置，显示/mnt为正常 2 mkdir test 创建test文件夹 输入ls命令,列出当前路径下内容，看到 test文件夹为正常 创建目录 3 cd /mnt/test 进入test文件夹 输入pwd命令查看当前位置，显示/mnt/test为正常 打开目录 4 touch test1.txt 创建test1.txt文件 输入ls命令,列出当前路径下内容，看到 test1.txt文件为正常 创建文件 5 vi test1.txt 打开编辑并保存文件 输入cat test1.txt查看test1.txt内容，与编辑内容一致为正常 读、写、关闭 6 rm test1.txt 删除了test1.txt 输入ls命令,列出当前路径下内容，未看到test1.txt为正常 删除文件 7 rm-rf/mnt/test 删除test文件夹 输入ls /mnt，列出/mnt下的所有内容，未看到test文件夹为正常 删除目录
Table 7.
Performance indicators of the storage module View tableView in ArticleTable 7.
Performance indicators of the storage module 序号 设计方法 存储空间/Tbit 数据记录速度/（Gbit·s-1） 数据回放速率/（Gbit·s-1） 控制平面 工作模式 操作系统 1 传统方法[ 4 ]30 4.8 4.8 RS422：115.2 kbit/s
CAN：1 Mbit/s
边读边写 不支持 2 本文方法 192 40.0 40.0 TTE接口：1 000 Mbit/s 边读边写、文件管理、坏块管理 支持Linux
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Yanqing WANG, Jinfeng ZHONG, Jie SHEN, Xunjiang ZHENG, Wenshan ZHU, Hua KONG. Design and Testing Verification of a High-capacity Spaceborne Storage Module Based on VPX Architecture for High-Speed Access[J]. AEROSPACE SHANGHAI, 2025, 42(3): 104
Paper Information
Category: Guidance, Navigation, Control and Electronics
Received: Aug. 15, 2024
Accepted: --
Published Online: Sep. 29, 2025
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