Gate data short (DGS) defects in IGZO TFT lead to deterioration of display performance and product scrap. It is necessary to identify the DGS mechanism, recognize the impact factors, and propose a solution to ensure the yield. In this paper, the macroscopic phenomena and microscopic morphology of DGS were analyzed. After that, the relationship between the dielectric loss of gate insulator ?(GI) and break-down voltage was explored. Then, the deterioration of display tests were conducted, and the DGS rate of different products was statistically analyzed, the effects of gate voltage and refresh rate on DGS rate were identified. Next, the experimental phenomenon is matched with the investigated DGS mechanism. Subsequently, the reasons for oxide TFT DGS being higher than a-Si TFT were analyzed. The results show that the essential of DGS is GI dielectric breakdown due to insufficient dielectric withstanding strength, while GI dielectric loss, gate voltage, and refresh rate are all the significant influencing factors of DGS. These factors, in the interaction of Cu diffusion and Cu electromigration mechanisms, reduce the GI effective thickness and increase the risk of GI thermal breakdown, which ultimately results in DGS. DGS can be suppressed by reducing thickness ratio of SiO_x in the stacked GI aiming at decreasing dielectric loss and inhibiting thermal breakdown; Alternatively, DGS is ultimately suppressed by decreasing gate voltage to inhibit Cu diffusion and electromigration. By introducing the above measures as an improvement plan, the incidence rate of DGS was decreased by 73%, which successfully suppressed the DGS rate of the oxide panel and improved the product quality, providing a reference for oxide TFT process optimization.