Fig. 1. Growth trends in Interconnection technology, GPU, and AI model compute

Fig. 2. Network architecture and interconnect methods in AI computing centers

Fig. 3. Schematic diagram of silicon photonic engine packaging and interconnects

Fig. 4. Frontier advances in silicon photonic engines. (a) CPO switch applications: Broadcom Bailly^[25], NVIDIA Spectrum-X/Quantum-X switches^[26]; (b) XPU applications: Ayar Labs TeraPHY^[28], Intel OCI^[29], Columbia University silicon photonic engines^[30]

Fig. 5. The whole flowchart of optoelectronic integrated chip collaborative design

Fig. 6. DFB of different structures. (a) Schematic of the long-cavity DFB from Casela^[31]; (b) structure of the double-groove ridge waveguide DFB from Tsinghua University^[32]; (c) structure of the asymmetric waveguide DFB from Chinese Academy of Sciences^[33]; (d) structure of the SOA-DFB from Lumentum Company^[34]; (e) structure of the SOA-DFB from Sumitomo Company^[35]

Fig. 7. Multi-wavelength lasers. (a) Micro-comb driving silicon photonic engine from Peking University^[36]; (b) quantum-dot FP comb laser from Innolume^[37]; (c) 8×8 MMI DFB array and 4λ DFB lasers from Intel^[38]; (d) multi-wavelength laser from Nanjing University^[39]

Fig. 8. EAM. (a) C-band silicon-germanium alloy EAM from IMEC^[40]; (b) O-band silicon-germanium QCSE EAM from IMEC^[41]; (c) silicon-germanium Franz Keldysh EAM with a bandwidth over 65 GHz from CUHK^[42]

Fig. 9. MZM. (a) The optical micrograph of the silicon slow light modulator from Peking University^[43]; (b) circuit topology and behavior of the proposed scheme from University of Southampton^[44]; (c) schematic of the designed modulator using distributed micro-capacitors from Laval University^[45]; (d) schematic of the distributed electrode Si PCW optical modulator from Yokohama National University^[46]; (e) schematic of the dual-segment TW-MZM-based CMRRM from Nokia Bell Lab^[47]; (f) configuration of the proposed silicon modulator using the tunable TFE from Zhejiang University^[48]

Fig. 10. MRM. (a) L-shaped doped MRM from Intel^[49]; (b) MRM with Q-factor of 26300 from Zhangjiang Laboratory^[51]; (c) MRM with 100% doping and bandwidth exceeding 67 GHz from XIOPM^[52]; (d) compact-sized vertical PN junction MRM from AMD^[53]; (e) interleaved electrode MDM from Columbia University^[54]; (f) MRM thermal control technology from Yonsei University^[55-56]

Fig. 11. Schematic structures of PIN PDs. (a) 265 GHz Ge-on-Si PIN PD from IHP^[57]; (b) Ge-on-Si PIN PD with inductor peaking from HUST^[58]; (c) Ge-on-Si APD with 700 pH inductor peaking from HUST^[59]; (d) lateral PIPN-type APD with 7078 GHz gain-bandwidth product from XIOPM^[60]

Fig. 12. Silicon photonic on-chip passive devices: (a) AWG from Zhejiang University^[65]; (b) mode division multiplexer based on multimode interferometers from Fudan University and Zhangjiang Laboratory^[66]; (c) grating coupler from Dalian University of Technology and IMEC^[67]; (d) edge coupler from Zhejiang University^[68]; (e) polarization-splitting grating coupler from IEF^[69]

Fig. 13. Different types of modulators. (a) Sub-pJ/b EAM driver from University of Delaware^[76]; (b) active feedback continuous-time linear equalization MZM driver from Institute of Semiconductors^[77]; (c) non-weighted linear MZM driver designed based on closed-form expression model from UCB^[78]; (d) dual-channel nonlinear equalization MRM driver compensating micro-ring nonlinearity from Intel^[79]; (e) stacked-driver-based MRM transmitter from Intel^[80]

Fig. 14. Two types of receivers. (a) A low-power 112 Gb/s receiver based on 130 nm BiCMOS technology from Southern University of Science and Technology^[81]; (b) a 56 Gb/s receiver integrating a 28 nm CMOS TIA and a Si-Ge APD from Texas A&M University^[82]

Fig. 15. Laser integration methods. (a) Disaggregated laser; (b) hybrid integration; (c) heterogeneous integration; (d) monolithic integration; (e) external laser source from Sumitomo Electric Industries^[85]; (f) photonic wire bonding from Freedom Photonics^[86]; (g) heterogeneously integrated quantum dot laser from Intel^[87]; (h) in-pocket quantum dot laser from UCSB^[88]

Fig. 16. Packaging Methods. (a) 2D integration from XIOPM^[91]; (b) 2.5D integration from Columbia University^[93]; (c) 3D integration from Columbia University^[30]; (d) monolithic integration from Institute of Semiconductors^[94]

Fig. 17. Next-generation silicon photonics process platform with thin-film lithium niobate/lithium tantalate and InP materials

Fig. 18. Accelerator. (a) The PACE accelerator by Lightelligence^[102]; (b) the photonic AI accelerator by Lightmatter^[103]