Fig. 1. Column readout with two buffers.

Fig. 2. Column readout with single buffer.

Fig. 3. (a) Proposed column readout. (b) Control timing of the proposed circuit.

Fig. 4. (a) Reset level sample phase. (b) Image level sample phase. (c) Reset level buffer phase. (d) Image level buffer phase.

Fig. 5. n columns readout schematic.

Fig. 6. Control timing of n columns readout.

Fig. 7. (Color online) Die micrograph.

Fig. 8. Output code and nonuniformity versus exposure time.

Fig. 9. Comparison of actual images before and after optimization. (a) Image with traditional technique. (b) Image with proposed technique.