[1] [1] BANERJEE D. PLL performance, simulation, and design[M]. 4th ed. [S.l.]: Dog Ear Publishing, 2006.

[4] [4] KROUPA V F. A high purity, high speed direct digital synthesizer[M]. Wiley: IEEE Press, 1999: 291-295. doi: 10.1109/9780470544396.ch39.

[6] [6] HASANNEZHAD M, JANNESARI A, LOTFIZAD M. Design of a high-frequency very low-power direct digital frequency synthesizer[J]. Journal of Circuits Systems & Computers, 2016, 25(8): 1650085. doi: 10.1142/S0218126616500857.

[7] [7] SUN Ying, LIANG Meiyin, XIE Teng. Design and improvement of a frequency synthesizer based on PLL+DDS+PLL[J]. Advances in Computer Science Research, 2017(62): 546-549.

[8] [8] OSADA M, XU Z L, IIZUKA T. A 3.2-to-3.8 GHz harmonic-mixer-based dual-feedback fractional-N PLL achieving -65 dBc in-band fractional spur[J]. IEEE Solid-State Circuits Letters, 2020(3): 534-537. doi: 10.1109/LSSC.2020.3037311.

[9] [9] ZHANG Yinghao, GAO Liuan, QI Longying, et al. DDS-PLL phased source for Ka-band beam control phased array receiver[C]//2018 the 12th International Symposium on Antennas, Propagation and EM Theory (ISAPE). Hangzhou, China: IEEE, 2018: 1-4. doi: 10.1109/ISAPE.2018.8634073.

[11] [11] MA B H, HO D, WANG Y P, et al. Highly integrated assembly processes solutions for double-sided-SiP package[C]//2020 IEEE The 8th Electronics System-Integration Technology Conference (ESTC). Tnsberg, Norway: IEEE, 2020: 1-5. doi: 10.1109/ESTC48849.2020.9229680.