Microelectronics, Volume. 52, Issue 1, 104(2022)

A Two-Stage-Protection SCR Device with Low Trigger Voltage

ZHANG Yingtao1, ZHU Zhihua1, FAN Xiaomei1, MAO Pan2, SONG Bin3, XU Qi’an3, WU Tiejiang3, CHEN Ruike1, WANG Yao1, and LIOU Juin Jei1
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
  • 3[in Chinese]
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    References(12)

    [1] [1] LAI D W, SQUE S, PETERS W, et al. Gate-lifted nMOS ESD protection device triggered by a p-n-p in series with a diode [J]. IEEE Trans Elec Dev, 2019, 66(4): 1642-1647.

    [2] [2] DU F B, HOU F, SONG W Q, et al. An improved silicon-controlled-rectifier (SCR) for low-voltage ESD application [J]. IEEE Trans Elec Dev, 2020, 67(2): 576-581.

    [3] [3] LIN C Y, FU W H. Diode string with reduced clamping voltage for efficient on-chip ESD protection [J]. IEEE Trans Dev Mater Reliab, 2016, 16(4): 688-690.

    [4] [4] SUN K M, LI T, MENG L Y. A modified CLTdSCR with low leakage and low capacitance for ESD protection [J]. IEEE Trans Elect Dev, 2021, 68(2): 934-937.

    [5] [5] DU F B, DONG X Y, YANG C J, et al. A robust dual directional SCR without current saturation effect for ESD applications [C] // IEEE 26th Int Symp Phys & Failure Analys Integr Circ. Hangzhou, China. 2019: 1-4.

    [6] [6] CHEN J T, KER M D. ESD protection design with diode-triggered quad-SCR for separated power domains [J]. IEEE Trans Dev & Mater Reliab, 2019, 19(2): 283-289.

    [7] [7] CHEN L, DU F B, CHEN R B, et al. Novel diode-triggered SCR with suppressed multiple triggering for ESD applications[C] // IEEE Int Conf EDSSC. Shenzhen, China. 2018: 1-2.

    [8] [8] LIANG H L, BI X W, GU X F, et al. Investigation on LDMOS-SCR with high holding current for high voltage ESD protection [J]. Microelec Reliab, 2016, 61(3): 120-124.

    [9] [9] ZHANG L Z, WANG Y, HE Y D. A novel technique to suppress multiple-triggering effect in typical DTSCRs under ESD stress [J]. IEICE Trans Elec, 2020, E103.C(5): 274-278.

    [10] [10] DU F B, HOU F, SONG W Q, et al. An enhanced MLSCR structure suitable for ESD protection in advanced epitaxial CMOS technology [J]. IEEE Trans Elec Dev, 2019, 66(5): 2062-2067.

    [11] [11] HUANG X Z, LIU Z W, LIU F, et al. High holding voltage SCRs with segmented layout for high-robust ESD protection [J]. Elec Lett, 2017, 53(18): 1274-1275.

    [13] [13] DU F B, SONG W Q, HOU F, et al. Augmented DTSCR with fast turn-on speed for nanoscale ESD protection applications [J]. IEEE Trans Elec Dev, 2020, 67(3): 1353-1356.

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    ZHANG Yingtao, ZHU Zhihua, FAN Xiaomei, MAO Pan, SONG Bin, XU Qi’an, WU Tiejiang, CHEN Ruike, WANG Yao, LIOU Juin Jei. A Two-Stage-Protection SCR Device with Low Trigger Voltage[J]. Microelectronics, 2022, 52(1): 104

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    Paper Information

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    Received: May. 20, 2021

    Accepted: --

    Published Online: Jun. 14, 2022

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.210186

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