Fig. 1. (a) Schematic diagram of programmable MZI. (b) Silicon photonic neural network based on MZI array with eight input ports and eight output ports.

Fig. 2. Single-layer optical interference and nonlinear element on artificial neural network.

Fig. 3. Patching transform of the CONV to GEMM.

Fig. 4. CDC maps the CONV into the MZI unit.

Fig. 5. High-level architecture of a general-purpose scalable photonic MZI-based NPU system.

Fig. 6. CDC input for saving bandwidth.

Fig. 7. (a) CDC-output photonic chip architecture and (b) CDC-input photonic chip architecture.

Fig. 8. End-to-end full flow simulator architecture.

Fig. 9. (a) Utilization of different MZI array sizes. (b) Normalized bandwidth and normalized perf/power of the NPU for different MZI sizes. (c) The accuracies of different DAC control bits.

Fig. 10. The photonic chip.

Fig. 11. (a) Setup server. (b) Server application test.