Chinese Journal of Liquid Crystals and Displays, Volume. 36, Issue 2, 279(2021)

Adaptive equalizer design based on CSPI protocol

ZHAO Bin1,2, ZHANG Yu-hua2, WANG Zhao2, and XU Feng-cheng2
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
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    References(10)

    [3] [3] FARJAD-RAD R, YANG C K K, HOROWITZ M A, et al. A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter [J]. IEEE Journal of Solid-State Circuits, 1999, 34(5): 580-585.

    [4] [4] GOTOH K, TAMURA H, TAKAUCHI H, et al. A 2B parallel 1.25 Gb/s interconnect I/O interface with self-configurable link and plesiochronous clocking [C]//Proceedings of 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. San Francisco, CA, USA: IEEE, 1999: 180-181.

    [5] [5] KUDOH Y, FUKAISHI M, MIZUNO M. A 0.13-μm CMOS 5-Gb/s 10-m 28AWG cable transceiver with no-feedback-loop continuous-time post-equalizer [J]. IEEE Journal of Solid-State Circuits, 2003, 38(5): 741-746.

    [6] [6] HWANG S, JUNG I, SONG J, et al. A 5.4 Gb/s adaptive equalizer with unit pulse charging technique in 0.13 μm CMOS [C]//Proceedings of 2012 IEEE International Symposium on Circuits and Systems. Seoul, South Korea: IEEE, 2012: 1959-1962.

    [7] [7] SEO J C, KIM T H, AN T J, et al. A high-speed adaptive linear equalizer with ISI level detection using periodic training pattern [C]//Proceedings of 2012 International SoC Design Conference. Jeju Island, South Korea: IEEE, 2012: 419-422.

    [8] [8] SHAKIBA M H. A 2.5 Gb/s adaptive cable equalizer [J]. Digest of Technical Papers of the Solid State Circuits Conference, 1999, 1(1): 396-397.

    [9] [9] CHOI J S, HWANG M S, JEONG D K. A 0.18-μm CMOS 3.5-Gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method [J]. IEEE Journal of Solid-State Circuits, 2004, 39(3): 419-425.

    [10] [10] YEN C S, FAZARINC Z, WHEELER R L. Time-domain skin-effect model for transient analysis of lossy transmission [J]. Proceedings of the IEEE, 1982, 70(7): 750-757.

    [11] [11] CAO W D, WANG Z Q, LI D M, et al. A 40 Gb/s adaptive equalizer with amplitude approaching technique in 65nm CMOS [C]//Proceedings of IEEE International Conference on Electron Devices and Solid-State Circuits. Singapore: IEEE, 2015.

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    ZHAO Bin, ZHANG Yu-hua, WANG Zhao, XU Feng-cheng. Adaptive equalizer design based on CSPI protocol[J]. Chinese Journal of Liquid Crystals and Displays, 2021, 36(2): 279

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    Paper Information

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    Received: Jun. 11, 2020

    Accepted: --

    Published Online: Mar. 30, 2021

    The Author Email:

    DOI:10.37188/cjlcd.2020-0147

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