Fig. 1. Equivalent circuit of a m-stage bipolar all-solid-state LTD

Fig. 2. Schematic of half sectional view of positive all-solid-state LTD

Fig. 3. Photo of the top view of an all-solid-state LTD module

Fig. 4. Schematic of pulse reset circuit

Fig. 5. Diagram of pulse reset current and bipolar LTD output pulse sequence

Fig. 6. Schematic of DC reset circuit

Fig. 7. Membrane equivalent circuit

Fig. 8. Test environment of bipolar all-solid-state LTD

Fig. 9. 1 ms, 1 A pulse reset current waveform

Fig. 10. 30 ms, 1 A pulse reset current waveform

Fig. 11. Different output voltage waveforms with DC and pulse reset current

Fig. 12. Different voltage waveforms with variable charging voltages

Fig. 13. Different output voltage waveforms with width variable

Fig. 14. Different output voltage waveforms with the number of parallel mosfet variable

Fig. 15. Different output voltage waveforms with pulse interval variable

Fig. 16. Different output voltage waveforms with DC reset current variable

Fig. 17. Different output voltage waveforms with secondary side variable

Fig. 18. Waveforms with output voltage of bipolar and MOSFET in negative module