Fig. 1. Basic principles of photodetection chips and structures of typical detectors^[11], where P is P-type layer, I is intrinsic layer, M is multiplication layer, and N is N-type layer. (a) A PN junction leverages the photoelectric effect for photoelectric conversion; (b) structure of a PIN-type photodetector; (c) structure of an avalanche photodiode (APD) detector; (d) structure of a unilateral carrier detector

Fig. 2. Relevant reports on spatial light surface-incidence photodetection chips. (a) High-speed surface-incidence photodetector with a germanium thin film on a silicon substrate^[16]; (b) vertical-structured photodetector array based on MAPbBr₃ microspheres^[17]; (c) time-space multiplexed optical computing architecture^[18]; (d) monocrystalline photodetector based on two-dimensional semiconductor grown on a sapphire substrate^[21]; (e) novel on-chip metasurface-enhanced mid-infrared photodetector^[23]; (f) PbS quantum dots thin-film surface-incidence photodetector^[24]

Fig. 3. Reports on the stacked alignment of photodetectors with normal incidence. (a) Schematic of a 3D photonic processor using 3D chip stacking and free-space optical interconnects^[25-26]; (b) schematic of stacked meta-MEMS chips and array configuration^[28]

Fig. 4. Relevant reports on waveguide-coupled photodetection chips. (a) III‒V photodetector with silicon-based waveguide coupling^[34]; (b) schematic of a waveguide-integrated van der Waals PN heterojunction photodetector^[35]; (c) epitaxial layer structure and band diagram of the reversely biased MUTC-PD^[42]; (d) fully analog chip combining electronic and photonic computing^[43]; (e) impedance-line-enhanced InP/InGaAs waveguide uni-traveling carrier photodetector^[45]; (f) perovskite/Si₃N₄ monolithically heterogeneous integrated chip-scale photonic system^[46]

Fig. 5. Architectures of photonic-electronic integrated chips. (a) Physical separation of detector arrays and processing circuits; (b) integration of photodetectors within memory and computing units

Fig. 6. Recent reports on integrated photodetection chips. (a) Schematic of an optical receiver implemented using 28 nm CMOS technology^[48]; (b) 8×8-channel optoelectronic readout array fabricated with TSMC’s 180 nm RF CMOS process^[49]; (c) monolithically integrated photonic computing chip system^[50]; (d) 3D-integrated optoelectronic system combining arrays of electronic units and photonic devices^[51]; (e) schematic corresponding to the cross-sectional view of a PD-RRAM unit^[54]; (f) schematic of optical and electrical stimulation on an OEM array^[55]