The exponential growth of data driven by big data and artificial intelligence is propelling data centers towards larger scales. The adoption of decoupled architectures has increased the number of interconnection nodes and data exchanges within these centers, particularly in new data centers tailored for artificial intelligence where distributed training requires a considerable data exchange between GPU nodes. Minimizing communication-to-computation ratio is crucial for efficient distributed machine learning frameworks. Despite using low-power, high-bandwidth optical interconnections for node-to-node data transfer, signal switching in data centers still relies heavily on a hierarchical structure of electrical switches. These traditional switches, constrained by bandwidth and port count, are inadequate for escalating demands of data transmission. Future high-performance, large-scale, and green data centers are likely to rely on optical switches offering high bandwidth, low latency, and minimal power consumption. Among various optical switch technologies, silicon photonic switching stands out due to its nanosecond-scale switching time, ultra-low power consumption, high integration potential, and compatibility with CMOS fabrication processes.

Scholars have focused on innovating silicon photonic switches configured in a cascaded Mach-Zehnder Interferometer (MZI) setup (refer to Table 1). The phase shift arm within the MZI structure, which modulates the refractive index through different mechanisms, primarily differentiates into electro-optic (EO) switches that leverage the carrier dispersion effect and thermo-optic (TO) switches that operate on thermal effects. Scaling port integration has been a central tenet in silicon photonic switch research, with advancements such as 32×32 EO switches achieved in 2017 and 64×64 TO switches in 2018, boasting rapid link switching time of approximately 1 ns. Generally, at equivalent scales, TO switches exhibit lower loss and superior crosstalk performance, while EO switches offer faster switching speeds and lower energy consumption due to their operational principles. Challenges remain in device calibration, optoelectronic hybrid packaging, and cumulative optical path loss management with network scaling, limiting the realization of larger-scale silicon photonic switches.

The development of large-scale silicon photonic switches hinges on key technologies such as network architecture optimization, unit device enhancement, loss compensation techniques, switch unit calibration, and optoelectronic hybrid packaging. These technologies are deeply interconnected and necessitate a balanced and integrated approach to achieve improvements. Network architecture forms the cornerstone for constructing large-scale optical switches, requiring comprehensive optimization that addresses switching path control, unit device calibration, and cumulative link loss. While unit device performance has nearly peaked, integrating III-V material devices to compensate for optical link losses poses technical challenges such as material integration and thermal management. Optoelectronic detectors or grating devices for monitoring and calibrating the switch unit states within integrated switch chips strain electrical packaging and raise practicality concerns in large-scale optical switch systems. System-level calibration methods hold promise but require validation for reliability. Optical and electrical packaging constraints present challenges during large-scale optical switch assembly, necessitating suitable optoelectronic hybrid packaging strategies considering network architecture, dimensions, optical coupling techniques, and control requirements.

The future demand for high-performance, large-scale green data centers underscores the development trajectory for silicon photonic switches. While silicon photonic technology is highly competitive in achieving low-power, large-scale optical switching devices, current loss and crosstalk performance must be further reduced to meet data center requirements. Progress in heterogeneous integration technologies, system-level unit device calibration methods, and advanced packaging technologies is expected to resolve bottleneck issues arising from increased device integration and calibration complexities. This progression paves the way for the realization of high-performance, highly integrated, and energy-efficient optical switches capable of supporting thousands of ports.