Fig. 1. Architecture and programming of the reconfigurable photonic processor. (a) The photonic processor consists of PSs and a waveguide network encoding the SSP instance {2, 3, 5, 7, 11, 13, 17}. Coherent light is injected into the network via one of the entries, and the evolution results are read out to give the solution. (b) Waveguide network in (a) can be represented by a network where lines denote optical paths, and nodes denote entry and four kinds of functional modules. The vertical (x direction) distance between two adjacent rows of hexagonal nodes is equal to the elements, as denoted by the integers on the left. Vertical (diagonal) movement of light means excluding (including) an element out of (into) the summation, whose value is denoted by the output port number of the light. The path highlighted in pink indicates that elements 3, 5, 11, and 13 are included, resulting in a sum 32. (c) Fixed split junctions equally split the light. (d) VS junctions can split the light with any specified ratio η:1−η(0≤η≤1) by properly setting the PSs. (e) Pass junctions preserve the original propagation of light. (f) Converge junctions gather together light from different paths. (g) A photonic processor initially designed for {X1,X2,…,XN} can be programmed by changing entry or/and tuning VS junctions.

Fig. 2. Computing results of the cases {2, 3, 5, 7, 11, 13, 17} and {2, 5, 7, 11, 13, 17}. (a) and (c) The experimental read-out displays as a line of spots, which certify the existence of the corresponding subset sums (i.e., the numbers below the spots). Sum 0 corresponds to the empty set. (b) and (d) The experimental and theoretical intensity distribution. The axis break is used for the joint display of logarithmic coordinates and zero intensity. In the theoretical cases, nonzero intensity certifies the existence of a subset sum. By applying a reasonable intensity threshold, the experimental signals can be correctly classified into valid (beyond the threshold) and invalid certifications (below the threshold, highlighted by the white solidus pattern). The tolerance intervals of the thresholds are marked by the bands filled with the black solidus, revealing the upper bounds and the lower bounds.

Fig. 3. Computing results of the cases {3, 5, 7, 11, 13, 17}, {5, 7, 11, 13, 17}, and {7, 11, 13, 17}. (a) The experimental read-out of the case {3, 5, 7, 11, 13, 17} and (b) the corresponding intensity distribution. The threshold applicable in our experiments has a considerably large tolerance interval, whose upper bound and lower bound are 0.00473 and 0.00025, respectively, as indicated by the band filled with the black solidus. (c) and (d) The experimental read-outs of the cases {5, 7, 11, 13, 17} and {7, 11, 13, 17}. The corresponding intensity distribution is presented in Fig. S6 in the Supplementary Material.

Fig. 4. Time–space consumption. (a) In the case of successive primes {2, 3, 5, 7, …}, our photonic processor is compared with representative electronic processors, which are released in 2001, 2020, and 2021. The electronic processors, which search the entire solution space to solve the SSP and have a run time of O(2N), are superior to the photonic processor at the early stage. However, the photonic processor gradually surpasses its electronic rivals, with a run time of O(N+q) where q is the sum of S. The curves encircled by dashed lines are magnified and displayed in (b). Clearly, the photonic processor has already outperformed all the electronic processors in our experimental demonstration where S={2,3,5,7,11,13,17}. (c) The estimated physical size of the optimized photonic processor. The set of size N=30 can be mapped to a silica glass chip of size 250mm×110mm, as indicated by the dashed lines.