Microelectronics, Volume. 54, Issue 1, 60(2024)

Design of a Low Power Clock Generator Based on Capacitor Charging and Discharging

DENG Jiaxiong and FENG Quanyuan
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  • [in Chinese]
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    References(5)

    [1] [1] YAN Y F, YAN T T, MO T T, et al. A 62 MHz~316 MHz phase-locked loop based on ring oscillator for ADC clock generator in 0.18 μm CMOS [C] // Third International Conference on Measuring Technology and Mechatronics Automation. Shanghai, China. 2011:6-8.

    [2] [2] JAHANGIR M Z. PAIDIMARRY C S. Design of a novel charge pump based current starved ring oscillator with reduced phase noise [C] // 2023 International Conference for Advancement in Technology (ICONAT). Goa, India. 2023: 1-3.

    [3] [3] WANG C C, SUNG T Y, YANG T Y, et al. A 50-MHz clock generator with voltage and temperature compensation using low dropout regulator [C] // 2013 International SoC Design Conference (ISOCC). Busan, South Korea. 2013: 99-102.

    [5] [5] HUANG J, TAO L, LI Z P. A low-jitter and low-power clock generator [C] // 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology. Shanghai, China. 2010: 385-387.

    [7] [7] YANG W B, WANG C H, CHUO I T. A robust oscillator for embedded system without external crystal [J]. Applied Mathematics & Information Sciences, 2015, 9(1): 73-80.

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    DENG Jiaxiong, FENG Quanyuan. Design of a Low Power Clock Generator Based on Capacitor Charging and Discharging[J]. Microelectronics, 2024, 54(1): 60

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    Paper Information

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    Received: Sep. 4, 2023

    Accepted: --

    Published Online: Aug. 7, 2024

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.230343

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