Fig. 1. Block diagram of the dTOF detector system

Fig. 2. Schematic of the dTOF detector readout circuit

Fig. 3. Quantification principle of the dTOF readout circuit

Fig. 4. Block diagram of multi-step calibratable histogram building

Fig. 5. Working flow diagram of the calibrated multi-step histogram. (a) Peak extraction; (b) peak calibration

Fig. 6. Micrograph of the dTOF detector chip

Fig. 7. Nonlinear errors of the TDC. (a) DNL; (b) INL

Fig. 8. Peak error calibration

Fig. 9. Dynamic characteristics test. (a) Single-shot precision; (b) extracted peak TOF value based on field programmable gate array (FPGA)

Fig. 10. Comparison of peak extraction rates for different histogram schemes

Fig. 11. Comparison of TOF value extraction accuracy for different histogram schemes

Fig. 12. Comparison of data memory capacity of different histogram schemes