The direct time-of-flight (dTOF) detector based on a single-photon avalanche diode (SPAD) demonstrates significant potential for applications in autonomous driving (AD), advanced driver assistance systems (ADAS), and 3D camera due to its high resolution and picosecond-level response. The dTOF detector is rapidly advancing towards higher array density, improved time resolution, and better detection accuracy. However, SPAD dark counts and background light noise can cause misfires, resulting in random errors in single TOF measurements. Therefore, multiple repeated TOF measurements and histogram construction are necessary for peak TOF extraction. Existing histogram methods suffer from large SRAM storage requirements, low detection accuracy, and slow processing rates, which can limit the development of the TOF array detectors. To address these issues, we propose a three-step hybrid dTOF detector fabricated using a 0.18 μm complementary metal oxide semiconductor (CMOS) process, along with a multi-step calibratable histogram algorithm for peak TOF detection. This approach provides high accuracy, small storage capacity, and fast processing, making it suitable for low-cost light detection and ranging (LiDAR) systems.

The dTOF detector (Fig. 1) comprises a SPAD array, a quenching circuit, and a readout circuit. The readout circuit (Fig. 2) includes a charge pump phase-locked loop (CPPLL), interpolators, and digital counters. The phase-locked loop (PLL) generates a 960 MHz high-frequency phase-locked loop clock by multiplying the input 30 MHz clock by 32. Interpolators interpolate the rising edges of the Start and Stop signals and control the transmitters to achieve phase locking. The coarse counter employs a linear feedback shift register (LFSR) structure to manage measurement dynamics, while the fine counter uses an asynchronous structure to ensure time resolution. The dTOF detector ultimately achieves a time resolution of 130 ps and a dynamic range of 258 ns. The multi-step calibratable histogram operates in peak TOF detection [Fig. 5(a)] and calibration [Fig. 5(b)] stages. Peak TOF detection involves a three-step extraction process where the most significant, middle, and least significant bits are progressively accumulated to obtain complete peak TOF data. A calibration function further reduces fixed errors.

The dTOF detector chip, fabricated using the 0.18 μm CMOS process, demonstrates linearity with differential nonlinearity (DNL) and integral nonlinearity (INL) within ±0.82 LSB (least significant bit) and ±0.98 LSB, respectively (Fig. 7). The fixed errors across the measurement range fluctuate between 30 ps and 345 ps (Fig. 8). The time accuracy of the dTOF detector with the multi-step calibratable histogram (MSCH) is tested using adjustable time interval pulses generated by a digital delay generator. The real peak TOF value is concentrated at 99.71 ns with a root mean square (RMS) of 193 ps [Fig. 9(a)]. Using the MSCH, the calibrated peak TOF is approximately 99.99 ns, achieving over 99% precision [Fig. 9(b)]. Comparisons among various histogram schemes show that the complete inter-frame histogram (CIFH) achieves the highest TOF peak extraction speed, while the partitioned inter-frame histogram (PIFH), folded inter-frame histogram (FIFH), and MSCH schemes show reductions of approximately 51%, 40%, and 22%, respectively. However, due to the reduction in storage space, the MSCH scheme has a certain improvement compared to the PIFH and FIFH schemes. In terms of peak extraction accuracy, the CIFH, PIFH, FIFH, and MSCH schemes achieve accuracies of 97.1%, 95.7%, 98.4%, and 99.9%, respectively (Fig. 11), demonstrating the high extraction accuracy of the proposed MSCH algorithm. The required SRAM storage capacity is compared, revealing that the MSCH scheme requires the least memory, with only 16 Mbit SRAM sufficient for a 256×256 high-density pixel array (Fig. 12).

A three-step hybrid structure dTOF detector has been realized using the 0.18 μm CMOS process. Test results indicate that the detector achieves high resolution of 130 ps and a large dynamic range of 258 ns with a low-jitter built-in PLL. The DNL and INL of the detector are within -0.82 LSB to 0.81 LSB and -0.96 LSB to 0.98 LSB, respectively. The MSCH algorithm processes TOF readout data effectively across different ranging distances. Compared to traditional CIFH, PIFH, and FIFH schemes, the MSCH algorithm significantly reduces SRAM storage capacity and achieves an extraction accuracy of 99.9%. Although the peak TOF extraction rate is slightly lower than that of CIFH, it still improves by a certain degree compared to PIFH and FIFH. The proposed dTOF detector and histogram algorithm demonstrate excellent performance, providing an alternative solution for high-density TOF array detectors with on-chip histograms.