Fig. 1. Phase noise of clock jitter and aperture jitter in the ADC sampling process

Fig. 2. Scheme of dual carrier phase measurement system

Fig. 3. Illustration of sampling jitter suppression system

Fig. 4. Procedure of data processing for the suppression of sampling jitter

Fig. 5. Residual noise in the suppression of aperture jitter

Fig. 6. Comparison of phase noise before and after sampling jitter correction