Fig. 1. Clock recovery structure based on Gardner algorithm

Fig. 2. Performance of the algorithm under different k₁. (a) BER; (b) convergence points

Fig. 3. Principle of the experimental system; (a) Flow chart; (b) laser source; (c) VCA; (d) coherent receiver; (e) ADC and FPGA circuit; (f) wiring result of FPGA

Fig. 4. Variation curve of BER with time when the jitter frequency is 1 mHz and the jitter range is -42---50 dBm

Fig. 5. Variation curve of BER with time when the lowest received power is -45 dBm. (a) 100 Hz; (b) 1 kHz

Fig. 6. Variation curve of BER with time when the lowest received power is -47 dBm. (a) 100 Hz; (b) 1 kHz

Fig. 7. Variation curve of BER with time when the lowest received power is -50 dBm. (a) 100 Hz; (b) 1 kHz