[2] [2] Christopher P R, Sathasivam S. Five-stage pipelined dualedge deblocking filter architecture for H. 265 video codec[J]. IEICE Electronics Express, 2019, 16(22): 500-510.

[3] [3] Pastuszak G, Abramowski A. Algorithm and architecture design of the H. 265/HEVC intra encoder[J]. IEEE Transactions on Circuits and Systems for Video Technology, 2015, 26 (1): 210-222.

[4] [4] Zhang Y Z, Lu C. Efficient algorithm adaptations and fully parallel hardware architecture of H. 265/HEVC intra encoder[J]. IEEE Transactions on Circuits and Systems for Video Technology, 2018, 29(11): 3415-3429.

[5] [5] Atapattu S, Liyanage N, Menuka N, et al. Real time all intra HEVC HD encoder on FPGA[C]//27th International Conference on Application-specific Systems, Architectures and Processors, 2016: 191-195.

[6] [6] Gu J Y, Yin S Y, Wei S J. Stress-aware loops mapping on CGRAs with dynamic multi-map reconfiguration[J]. IEEE Transactions on Parallel and Distributed Systems, 2018, 29 (9): 2105-2120.

[7] [7] Cabigao N, Gonzaga M, Alvarez H, et al. Design of multiple prediction complexity configurations for an FPGA-based H. 264 baseline profile encoder[C]//TENCON 2018－2018 IEEE Region 10 Conference, 2018: 1727-1732.

[8] [8] Zhu Y, Jiang L, Shi P, et al. Parallelization of intra prediction algorithm based on array processor[J]. High Technology Letters, 2019, 25(1): 74-80.

[9] [9] Shan R, Jiang L, Wu H Y, et al. Dynamical self-reconfigurable mechanism for data-driven cell array[J]. Journal of Shanghai Jiaotong University, 2021, 26(7): 511-521.

[10] [10] Zhang Y Z, Lu C. High-performance algorithm adaptations and hardware architecture for HEVC intra encoders[J]. IEEE Transactions on Circuits and Systems for Video Technology, 2019, 29(7): 2138-2145.

[11] [11] Deng J Y, Jiang L, Zhu Y, et al. HRM: H-tree based reconfiguration mechanism in reconfigurable homogeneous PE array[J]. Journal of Semiconductors, 2020, 41(2): 22402

[13] [13] Wang H L, Xiao B, Wu J, et al. A collaborative scheduling-based parallel solution for HEVC encoding on multicore platforms[J]. IEEE Transactions on Multimedia, 2018, 20 (11): 2935-2948.

[14] [14] Kammoun A, Hamidouche W, Philipp P, et al. Hardware acceleration of approximate transform module for the versatile video coding standard[C]//27th European Signal Processing Conference, 2019: 1-5.

[15] [15] Lu Y N, Liu L B, Zhu J F, et al. Architecture, challenges and applications of dynamic reconfigurable computing[J]. Journal of Semiconductors, 2020, 41(2): 21401.

[16] [16] Porto R, Correa M, Goebel J, et al. UHD 8K energy-quality scalable HEVC intra-prediction SAD unit hardware using optimized and configurable imprecise adders[J]. Journal of Real-Time Image Processing, 2020, 17(5): 1685-1701.

[17] [17] Baldev S, Rathore P K, Peesapati R, et al. A directional and scalable streaming deblocking filter hardware architecture for HEVC decoder[J]. Microprocessors and Microsystems, 2021, 84: 104029.

[18] [18] Feng Z Q, Liu P Y, Jia K B, et al. HEVC fast intra coding based CTU depth range prediction[C]//3rd International Conference on Image, Vision and Computing, 2018: 551-555.

[19] [19] Venkatesh A, Karanth P, Talawar K. An efficient FPGA based reconfigurable architecture for object detection using adaptive threshold[C]//4th International Conference on Electrical, Electronics, Communication, Computer Technologies and Optimization Techniques, 2019: 234-239.

[20] [20] Koraol G, Jordan M G, Brandalero M, et al. MCEA: A resource-aware multicore CGRA architecture for the edge[C]//30th International Conference on Field-Programmable Logic and Applications, 2020: 33-39.