During the hardware implementation of the high efficiency video coding standard (HEVC), its high computational complexity and high data dependence not only hinder the performance of real-time video encoding, but also bring higher resource consumption. In this paper, we analyzed the data/timing dependency relationship between the various algorithms of the intra-frame loop when processing pixel blocks, and the HEVC intra-loop reconfigurable array structure based on the variable coding block pipeline is completed. By using the adjacent interconnection interface between the modules, the handshake communication realized the pipeline processing between the entire intra-frame loop coding blocks, and improved the calculation efficiency of the intra-frame loop. The experimental results show that the proposed method meets the requirements of computing speed and hardware resources. Compared with the serial-based intra-loop encoding processing circuit, the execution time is reduced by 87%, and the clock frequency reaches 125 MHz.