Depletion-type silicon ring modulators (Si RMs) attract a great amount of research interests since they can provide advantages for optical interconnect (IC) applications such as large modulation bandwidth and small power consumption ^[1–4]. Furthermore, Si RMs are much smaller than the widely used Si Mach–Zehnder modulators (MZMs) and, consequently, allow much easier monolithic integration with electronics. Such electronic–photonic integration is necessary for interconnection solutions for future high-performance electronic systems in which photonic solutions must be as closely located to electronics as possible for size and power consumption reduction ^[5]. To realize Si electronic–photonic ICs containing Si RMs, a Si RM equivalent circuit model that is accurate, easy-to-use, and compatible with the standard IC design environment is highly desirable. In addition, extracting numerical values for model parameters should be simple and straight-forward.

Although there have been several published reports on depletion-type Si RM models, none satisfies the above requirements. In Ref. ^[6], a precise analytical model for a Si RM was reported, but it requires more than 10 parameters and is not very compatible with the standard Si IC design environment. We reported a Verilog-A implementation of a coupled-mode description of the Si RM ^[7], which can be easily executed in the SPICE simulation environment. It, however, requires a substantial amount of computation time because Verilog-A is not optimized for numerically solving differential equations and, consequently, the simulation must use a very fine time resolution to accurately describe Si RM dynamics.

In this paper, we present a large-signal equivalent circuit model based on the linear equivalent circuit of the Si RM ^[8], which contains only a few independent model parameters that can be easily extracted from the simple RM transmission measurement. Although model parameter values nonlinearly depend on the Si RM bias voltage, we demonstrate that, by using voltage-dependent circuit elements available within SPICE, large-signal transient modulation characteristics can be easily and accurately simulated at least 220 times faster than the approach used in Ref. ^[7]. Such a reduction in computation time should provide a great advantage for design optimization of optical interconnection solutions for high-performance electronic systems that may contain numerous Si RMs as well as various electronic circuit blocks. An initial portion of this work was reported in Ref. ^[9]. In this paper, a more detailed description of our model is presented. In addition, we provide how our model can be used for performance optimization of pulse-amplitude modulation 4 (PAM-4) transmitters containing Si RMs and SiGe BiCMOS transistors.

This paper is organized in four chapters. In Chapter 2, after a brief description of the Si RM device used for our investigation, we give the details of our model and explain how model parameters are extracted from measurement results. The accuracy of the model also is verified with a 25 Gb/s non-return-to-zero (NRZ) measurement. In Chapter 3, we demonstrate the advantage of our model by showing how it can be used for the design optimization of a monolithic Si photonic NRZ and PAM-4 transmitters in terms of power consumption minimization and optical modulation amplitude (OMA) maximization. Chapter 4 concludes the paper.

Figure 1(a) shows the structure of the depletion-type Si RM used for our investigation. It is fabricated by a Si photonics foundry service provided by IHP. The ring has an 8 μm radius, and there is a 290 nm separation between the bus and ring waveguides, as can be seen in the TEM image of the cross-section of the coupling section given in Fig. 1(b). The lateral p-n junction diode for the ring waveguide has the nominal peak doping concentration of 7×1017cm−3 for the p-region and 3×1018cm−3 for the n-region. Figure 1(c) shows the normalized transmission characteristics measured at four different bias voltages. For this and other measurements reported in this paper, the device is placed on a stage whose temperature is maintained at 25°C by a temperature controller.

The dynamic characteristics of an RM can be described by coupled-mode equations as ^[10] where a(t) represents the energy stored in the ring resonator, and τ is the decay time constant for a(t). τ has two components, τl and τe, which, respectively, represent the decay time constants due to the ring resonator loss and the coupling loss between the ring and bus waveguides. Their relationship is given as 1τ=1τl+1τe. ωres is the ring resonance angular frequency given as ωres=2πmcneffL, where m is an integer representing the resonance mode index, c is the velocity of light in the vacuum, L is the ring circumference, and neff is the effective index of the ring waveguide at the resonance.

The RM steady-state transmission characteristics can be derived from Eqs. (1) and (2) as By fitting Eq. (3) to the measured transmission characteristics shown in Fig. 1(c), numerical values for three key parameters (neff, τ, τl) at different bias voltages can be determined. The results are given in Table 1. The quality factor of the RM is related to τ as Q=ωresτ2, which indicates our RM has a Q of about 8000.

The normalized RM small-signal modulation frequency response in the s-domain at a given bias voltage can be approximated as ^[11] where Dω is the detuning parameter (Dω=|ωin−ωres|) representing how much the input light frequency (ωin) is separated from the RM resonance frequency (ωres). Figure 2(a) shows the block diagram of the Si RM equivalent circuit. It consists of three blocks. Block A accounts for parasitic RLC components due to bond pads and metal interconnects ^[8]. Block B shown in Fig. 2(b) represents the RM’s electrical property due to a series resistance and ring waveguide p-n junction. Block C shown in Fig. 2(c) is an equivalent circuit emulating Eq. (4). Voltage-dependent resistors and capacitors are used in Blocks B and C, as the junction capacitance, and τ and τl depend on RM bias voltages. A scaling factor given as g=PoutPin·R1+R2R2 is used in Block C, where Pin and Pout are the input and output optical power used for the RM transmission measurement, respectively, so that Block C output voltage, Vout, represents the ratio of Pout and Pin.

Numerical values for circuit elements in Blocks A and B can be easily obtained from the electrical s-parameter measurements at different bias voltages. Numerical values for Block C circuit elements are obtained by matching Eq. (4) with the Block C transfer function given as using extracted numerical values for neff, τ, and τl at different bias voltages and detuning values. Table 2 shows the extracted numerical values for Block C circuit elements for two different cases of detuning wavelengths. The circuit models given in Block B and Block C are small signal models whose parameter values depend on bias voltages. With parameter values determined at a few sample bias voltages, large-signal behavior modeling can be easily done using the piece-wise linear simulation capability available in SPICE. Here, the detuning wavelength given as Dλ=2πcDω is used because it is more convenient to use in measurement. As can be seen in the table, Rs is independent of the bias voltage and detuning, and Cj is independent of detuning. Since Eq. (4) has three independent variables (τl,τ,Dω) and Eq. (5) has four (R1,R2,L,C), we arbitrarily fix the value of R2 at a 0 bias voltage as 10,000 Ω and then determine other circuit parameter values at the same bias voltages. For other bias voltages, we fix the value of L at the value determined at 0 bias voltage and modify other resistor and capacitor values since variable resistors and capacitors are much easier to use in SPICE than the variable inductor. R2 does not change with Dλ since τl does not depend on Dλ. On the other hand, R1 is proportional to Dλ, and R1C is proportional to τe, which does not depend on Dλ. Consequently, C decreases with Dλ.

The voltage-dependent circuit elements in Fig. 2(b) can be easily implemented with the piece-wise linear (PWL) elements available in SPICE. Using this approach, the large-signal RM eye diagrams can be very easily simulated in SPICE. Although parameter values at only five different biases are specified for our investigation, the simulator automatically interpolates the values at other bias voltages, providing very accurate and efficient simulation results. Figure 3 shows both the measured and simulated (red lines) 25 Gb/s Si RM eye diagrams for several detuning values. For both, modulating signals are 231−1 PRBS having 4Vpeak−to−peak with −2V common mode voltage. For simulation, Synopsys HSPICE, Version M 2017.03, is used. In addition, S21 responses of RF cables, the oscilloscope (Tektronix CSA8000B and 80E03), and the optical receiver (Optilab PR-23-M) ^[12] used in the measurement are included to achieve an accurate comparison. As can be seen, the simulation based on the RM equivalent circuit provides good agreement with the measurement results. For a 1 μs long transient simulation with a 0.1 ps time step, the approach reported in Ref. ^[7] requires 980 s in computation with two octa-core Intel processors (E5-2640 v3) and 32 GB RAM, whereas our new approach needs only 4.43 s in the same computation environment, providing performance that is 220 times faster. As can be seen in Fig. 3, data with Dλ as 70 pm shows the largest OMA.

The real advantage of our model is the ease with which it can be used for co-simulation of electronic circuits and Si RMs. Figure 4(a) shows a schematic diagram for an integrated 25 Gb/s Si photonic transmitter containing a fully differential cascode common-emitter driver and a Si RM. The driver employs the source degeneration technique with RE to enhance the transmitter bandwidth. This kind of electronic–photonic integrated circuits can be monolithically fabricated with IHP’s photonic BiCMOS technology, which provides high-performance SiGe bipolar transistors having fT/fmax of 220/290-GHz and Si photonic components on the same Si platform ^[13]. With our RM circuit model, the design optimization of the entire transmitter can be easily carried out.

Figure 4(b) shows the simulated vertical eye opening normalized to the input optical power at different values of Itail and RL for the case of Dλ=70pm to have the largest OMA. Itail and RL are key parameters in the driver that determine eye opening, power consumption, and bandwidth. For the simulation, 25 Gb/s 231−1 PRBS NRZ data with a 600 mV swing are supplied to Vin+ and Vin−. Also, the power supply of the driver circuit (Vcc) was 4.5 V to have the output data of the driver circuit as 4Vpeak−to−peak. Post-layout parasitic RC values for the driver are included in the simulation since they can significantly influence the driver performance. As can be seen in Fig. 4(b), the vertical eye opening strongly depends on RL and Itail values. The optimal condition can be determined that provides the largest modulator output eye opening with the smallest Itail, or the smallest power consumption. With a fixed value for RL, larger Itail generates a larger output voltage swing but runs into the headroom problem if Itail is too large. Figure 4(c) shows simulated eye diagrams at three different conditions, whose Itail and RL values are represented by Points A, B, and C in Fig. 4(b), having 4Vpeak−to−peak at the driver output. Point A requires a small Itail for peak eye opening but experiences degradation due to a large RC time constant, as shown in the simulated eye diagram. Points B and C show similar eye patterns in terms of rising and falling times but Point C requires a larger Itail due to a smaller RL, which results in a larger power consumption. Consequently, Point B provides the largest eye opening with the smallest power consumption.

Our RM circuit model can also be used to optimize the ratio of level mismatch (RLM), which is the key performance parameter for a PAM-4 transmitter. RLM is defined as where ΔVupper, ΔVmid, and ΔVlower are defined in Fig. 5. PAM-4 allows a higher data rate transmission without requiring a higher transmitter bandwidth, and it is the standard for many important high-speed I/O applications ^[14,15]. There is growing interest in PAM-4 based on Si RMs ^[16–20], but its performance is greatly affected by Si RM nonlinearity, which results in degraded RLM ^[16–20]. This nonlinearity is due to the Lorentzian shape of the RM resonance as well as the nonlinear dependence of the ring waveguide effective index on the reverse bias ^[20]. This poses a great challenge to achieve Si PAM-4 transmitters because there is a rather tight requirement on RLM. RLM higher than 94%, for example, is required for IEEE802.3bs and CEI-56G ^[14,15]. One solution is to apply different driving voltages for ΔVupper, ΔVmid, and ΔVlower, which can compensate for RM nonlinearity ^[20,21]. To use this approach, an accurate co-simulation of a driver circuit and RM is essential.

Figure 6(a) shows a schematic diagram for an integrated 25 GBaud PAM-4 Si photonic transmitter containing a Si RM and a fully differential cascode BiCMOS common-emitter driver with the emitter degeneration based on IHP photonic BiCMOS technology. To determine the optimum PAM-4 modulation condition, SPICE simulation is performed for the integrated transmitter for varying RM Dλ values and different RLM values for the driver output voltages measured between VDRV (RLMDRV). For the simulation, RL=80Ω is selected based on the optimization carried out for the above-mentioned NRZ transmitter. Data (25 Gb/s 231−1 PRBS NRZ) is supplied to both inputs of MSB and LSB ports.

The entire transmitter, including the driver and the Si RM, is simulated using the equivalent circuit for Si RM. Figure 6(b) shows the resulting RLM for the Si RM output, or RLMRM for varying driver output voltage RLM, or RLMDRV, and detuning. Different RLMDRV values are achieved by changing ILSB and IMSB, while their sum is kept the same and VDRV has a 4Vpeak−to−peak swing. As can be seen in the figure, RLMRM over 94% can be achieved when Dλ is about 80 pm and the RLMDRV is between about 75% and 85%. Figure 7 shows the simulated eye diagrams for the driver and RM outputs in different conditions represented by Points A, B, C, and D in Fig. 6(b), and such conditions and results are described in Table 3. At Point A, RLMDRV is almost 100% but RLMRM is significantly degraded due to Si RM nonlinearity. The RM nonlinearity is such that the middle eye opening is the largest. Consequently, by distorting driver output or making the middle eye smaller, RLMRM can be improved, as shown by the Points B and C eye diagrams. Too much driver output distortion causes RLMRM degradation, as shown by the Point D eye diagram. With the optimum distortion of the driver output, we can carefully choose the detuning for the maximum RLMRM, as Point C shows an almost 97% RLM value.

We demonstrate a new large-signal SPICE circuit model for a depletion-type Si RM. The model is accurate, easy to use, and allows a significantly reduced simulation time compared to the previously reported approach. The accuracy of the model is confirmed with measured 25 Gb/s NRZ modulation results at different detuning values. Furthermore, the model allows easy co-simulation with electronic driver circuits. We demonstrate the design optimization based on such co-simulation for Si NRZ and PAM-4 transmitters containing SiGe BiCMOS drivers and Si RMs.

Acknowledgment. We thank IC Design Education Center (IDEC) for EDA tool support.