Microelectronics, Volume. 52, Issue 2, 265(2022)

A Sampling Distortion Cancellation Circuit for High Precision SAR ADC

CHEN Shangcun... DENG Honghui, CHEN Chaochao and YIN Yongsheng |Show fewer author(s)
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    References(10)

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    [3] [3] WANG J C, HUNG T C, KUO T H. A calibration-free 14-b 07-mW 100-MS/s pipelined-SAR ADC using a weighted-averaging correlated level shifting technique [J]. IEEE J Sol Sta Circ, 2020, 55(12): 3271-3280.

    [4] [4] YU Q, ZHOU X, HU K, et al. A 908 ENOB 10 b 400 MS/s subranging SAR ADC with subsetted CDAC and PDAS in 40 nm CMOS [C]// IEEE 47th ESSCC. Grenoble, France. 2021: 391-394.

    [8] [8] CHEN H, ZHOU X, YU Q, et al. A >3 GHz ERBW 11 GS/s 8 b two-step SAR ADC with recursive-weight DAC [C]// IEEE Symp VLSI Circ. Honolulu, HI, USA. 2018: 97-98.

    [9] [9] LIU C C, CHANG S J, HUANG G Y, et al. A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure [J]. IEEE J Sol Sta Circ, 2010, 45(4): 731-740.

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    CHEN Shangcun, DENG Honghui, CHEN Chaochao, YIN Yongsheng. A Sampling Distortion Cancellation Circuit for High Precision SAR ADC[J]. Microelectronics, 2022, 52(2): 265

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    Paper Information

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    Received: Feb. 20, 2022

    Accepted: --

    Published Online: Jan. 16, 2023

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.zjea024

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