Journal of Semiconductors, Volume. 41, Issue 11, 111404(2020)

A survey of high-speed high-resolution current steering DACs

Xing Li1,2 and Lei Zhou2
Author Affiliations
  • 1University of Chinese Academy of Sciences, Beijing 100049, China
  • 2Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, China
  • show less
    References(68)

    [1]

    [2] S Spiridon, J Tang, H Yan et al. A 375 mW multimode DAC-based transmitter with 2.2 GHz signal bandwidth and in-band IM3 < –58 dBc in 40 nm CMOS. IEEE J Solid State Circuits, 48, 1595(2013).

    [3]

    [4] J Xiao, B Chen, T K Kim et al. A 13-bit 9GS/s RF DAC-based broadband transmitter in 28nm CMOS. IEEE Symposium on VLSI Circuits, 262(2013).

    [5] P C Ku, K Y Shih, L H Lu. A high-voltage DAC-based transmitter for coded signals in high frequency ultrasound imaging applications. IEEE Trans Circuits Syst I, 65, 2797(2018).

    [6] C Erdmann, B Verbruggen, B Vaz et al. A modular 16nm direct-RF TX/RX embedding 9GS/S DAC and 4.5GS/S ADC with 90dB isolation and sub-80PS channel alignment for monolithic integration in 5G base-station SoC. 2018 IEEE Symposium on VLSI Circuits, 219(2018).

    [7]

    [8] A Roshan-Zamir, B Wang, S Telaprolu et al. A two-segment optical DAC 40 Gb/s PAM4 silicon microring resonator modulator transmitter in 65nm CMOS. IEEE Optical Interconnects Conference (OI), 5(2017).

    [9] W Z Li, L Zhou, M Luo et al. 100Gb/s/λ optical fiber transmission based on high speed DAC in SiGe technology. 2018 Conference on Lasers and Electro-Optics Pacific Rim, 1(2018).

    [10] P Ostrovskyy, O Schrape, K T Helmric et al. A radiation hardened 16 GS/s arbitrary waveform generator ic for a submillimeter wave chirp-transform spectrometer. 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 1(2018).

    [11] F Van de Sande, N Lugil, F Demarsin et al. A 7.2 GSa/s, 14 bit or 12 GSa/s, 12 bit signal generator on a chip in a 165 GHz fT BiCMOS process. IEEE J Solid-State Circuits, 47, 1003(2012).

    [12]

    [13] Y Zhuang, B Magstadt, T Chen et al. High-purity sine wave generation using nonlinear DAC with predistortion based on low-cost accurate DAC–ADC co-testing. IEEE Trans Instrum Meas, 67, 279(2018).

    [14] J S Hansen, G Jue. New approach to spectrum and emitter simulation: For the evaluation of radar and electronic warfare systems. 2013 International Conference on Radar, 532(2013).

    [15] A Glascott-Jones, N Chantier, F Bore et al. Direct conversion to X band using a 4.5 GSps SiGe digital to analog converter. 2014 International Radar Conference, 1(2014).

    [16] Y Yao, F Dai, R C Jaeger et al. A 12-bit cryogenic and radiation-tolerant digital-to-analog converter for aerospace extreme environment applications. IEEE Trans Ind Electron, 55, 2810(2008).

    [17] C H Lin, K L J Wong, T Y Kim et al. A 16b 6GS/S Nyquist DAC with IMD < –90dBc up to 1.9GHz in 16nm CMOS. 2018 IEEE International Solid-State Circuits Conference (ISSCC), 360(2018).

    [18] A van den Bosch, M A F Borremans, M S J Steyaert et al. A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter. IEEE J Solid-State Circuits, 36, 315(2001).

    [19] B C Kim, M H Cho, Y G Kim et al. A 1 V 6-bit 2.4 GS/s Nyquist CMOS DAC for UWB systems. 2010 IEEE MTT-S International Microwave Symposium, 912(2010).

    [20] F T Chou, C M Chen, Z Y Chen et al. A novel glitch reduction circuitry for binary-weighted DAC. 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 240(2014).

    [21] C H Lin, F M L van der Goes, J R Westra et al. A 12 bit 2.9 GS/s DAC with IM3 < < –60 dBc beyond 1 GHz in 65 nm CMOS. IEEE J Solid-State Circuits, 44, 3285(2009).

    [22] Y H Gong, R L Geiger. Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays. IEEE Trans Circuits Syst II, 47, 585(2000).

    [23] H Chen, L Y Liu, D M Li et al. A 12-bit current steering DAC with 2-dimensional gradient-error tolerant switching scheme. J Semicond, 31, 105006(2010).

    [24] D A Mercer. Low-power approaches to high-speed current-steering digital-to-analog converters in 0.18-μm CMOS. IEEE J Solid-State Circuits, 42, 1688(2007).

    [25] H H Chen, J Lee, J Weiner et al. A 14-b 150 MS/s CMOS DAC with digital background calibration. 2006 Symposium on VLSI Circuits, 51(2006).

    [26] M Clara, W Klatzer, B Seger et al. A 1.5V 200MS/s 13b 25mW DAC with randomized nested background calibration in 0.13μm CMOS. 2007 IEEE International Solid-State Circuits Conference, 250(2007).

    [27]

    [28] H Y Zhu, W H Yang, G Engel et al. A two-parameter calibration technique tracking temperature variations for current source mismatch. IEEE Trans Circuits Syst II, 64, 387(2017).

    [29] S H Xu, J W Lee. Calibration and correction of timing mismatch error in two-channel time-interleaved DACs. 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1(2019).

    [30] W T Lin, H Y Huang, T H Kuo. A 12-bit 40 nm DAC achieving SFDR > 70 dB at 1.6 GS/s and IMD –61dB at 2.8 GS/s with DEMDRZ technique. IEEE J Solid-State Circuits, 49, 708(2014).

    [31]

    [32] E Bechthum, G I Radulov, J Briaire et al. A wideband RF mixing-DAC achieving IMD < –82 dBc up to 1.9 GHz. IEEE J Solid-State Circuits, 51, 1374(2016).

    [33] S Su, M S Chen. A 12-Bit 2 GS/s dual-rate hybrid DAC with pulse-error predistortion and in-band noise cancellation achieving > 74 dBc SFDR and < –80 dBc IM3 up to 1 GHz in 65 nm CMOS. IEEE J Solid-State Circuits, 51, 2963(2016).

    [34] S Park, G Kim, S C Park et al. A digital-to-analog converter based on differential-quad switching. IEEE J Solid-State Circuits, 37, 1335(2002).

    [35] H Huang, T Kuo. A 0.07-mm2 162-mW DAC achieving > 65 dBc SFDR and < –70 dBc IM3 at 10 GS/s with output impedance compensation and concentric parallelogram routing. IEEE J Solid-State Circuits, 55, 2478(2020).

    [36] C Erdmann, E Cullen, D Brouard et al. A 330mW 14b 6.8GS/s dual-mode RF DAC in 16nm FinFET achieving –70.8dBc ACPR in a 20MHz channel at 5.2GHz. 2017 IEEE International Solid-State Circuits Conference (ISSCC), 280(2017).

    [37] V Ravinuthula, W Bright, M Weaver et al. A 14-bit 8.9GS/s RF DAC in 40nm CMOS achieving >71dBc LTE ACPR at 2.9GHz. 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 1(2016).

    [38]

    [39]

    [40] S Y Su, M S W Chen. A 16-bit 12-GS/s single-/dual-rate DAC with a successive bandpass delta-sigma modulator achieving <–67-dBc IM3 within DC to 6-GHz tunable passbands. IEEE J Solid-State Circuits, 53, 3517(2018).

    [41]

    [42]

    [43] A Nazemi, K M Hu, B Catli et al. 3.4 A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS. 2015 IEEE International Solid-State Circuits Conference (ISSCC), 1(2015).

    [44] Y M Greshishchev, D Pollex, S C Wang et al. A 56GS/S 6b DAC in 65nm CMOS with 256×6b memory. 2011 IEEE International Solid-State Circuits Conference, 194(2011).

    [45] J P Carreira. A two-step flash ADC for digital CMOS technology. Second International Conference on Advanced A-D and D-A Conversion Techniques and their Applications, 48(1994).

    [46]

    [47] C H Lin, K Bult. A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2. IEEE J Solid-State Circuits, 33, 1948(1998).

    [48]

    [49] S Y Su, T I Tsai, P K Sharma et al. A 12 bit 1 GS/s dual-rate hybrid DAC with an 8 GS/s unrolled pipeline delta–sigma modulator achieving > 75 dB SFDR over the nyquist band. IEEE J Solid-State Circuits, 50, 896(2015).

    [50] B Schafferer, R Adams. A 3V CMOS 400mW 14b 1.4GS/s DAC for multi-carrier applications. 2004 IEEE International Solid-State Circuits Conference, 360(2004).

    [51] A R Bugeja, B S Song, P L Rakers et al. A 14-b, 100-MS/s CMOS DAC designed for spectral performance. IEEE J Solid-State Circuits, 34, 1719(1999).

    [52] M J Choe, K H Baek, M Teshome. A 1.6-GS/s 12-bit return-to-zero GaAs RF DAC for multiple Nyquist operation. IEEE J Solid-State Circuits, 40, 2456(2005).

    [53] L Duncan, B Dupaix, J J McCue et al. A 10-bit DC-20-GHz multiple-return-to-zero DAC with >48-dB SFDR. IEEE J Solid-State Circuits, 52, 3262(2017).

    [54]

    [55]

    [56]

    [57] X Q Li, Q Wei, Z Xu et al. A 14 bit 500 MS/s CMOS DAC using complementary switched current sources and time-relaxed interleaving DRRZ. IEEE Trans Circuits Syst I, 61, 2337(2014).

    [58]

    [59] D Wang, L Zhou, D Y Wu et al. An 8 GSps 14 bit RF DAC with IM3 < –62 dBc up to 3.6 GHz. IEEE Trans Circuits Syst II, 66, 768(2019).

    [60] Q T Huang, P A Francese, C Martelli et al. A 200MS/s 14b 97mW DAC in 0.18μm CMOS. 2004 IEEE International Solid-State Circuits Conference, 364(2004).

    [61] H T Jensen, I Galton. A low-complexity dynamic element matching DAC for direct digital synthesis. IEEE Trans Circuits Syst II, 45, 13(1998).

    [62] T. Kuo T. Lin W. A compact dynamic-performance-improved current-steering DAC with random rotation-based binary-weighted selection. IEEE J Solid-State Circuits, 47, 444(2012).

    [63]

    [64] G A M Van Der Plas, J Vandenbussche, W Sansen et al. A 14-bit intrinsic accuracy Q2 random walk CMOS DAC. IEEE J Solid-State Circuits, 34, 1708(1999).

    [65] W H Tseng, J T Wu, Y C Chu. A CMOS 8-bit 1.6-GS/s DAC with digital random return-to-zero. IEEE Trans Circuits Syst II, 58, 1(2011).

    [66] W H Tseng, C W Fan, J T Wu. A 12-Bit 1.25-GS/s DAC in 90 nm CMOS with > 70 dB SFDR up to 500 MHz. IEEE J Solid-State Circuits, 46, 2845(2011).

    [67]

    [68] L Q Lai, X Q Li, Y S Fu et al. Demystifying and mitigating code-dependent switching distortions in current-steering DACs. IEEE Trans Circuits Syst I, 66, 68(2019).

    Tools

    Get Citation

    Copy Citation Text

    Xing Li, Lei Zhou. A survey of high-speed high-resolution current steering DACs[J]. Journal of Semiconductors, 2020, 41(11): 111404

    Download Citation

    EndNote(RIS)BibTexPlain Text
    Save article for my favorites
    Paper Information

    Category: Reviews

    Received: Jun. 29, 2020

    Accepted: --

    Published Online: Sep. 10, 2021

    The Author Email:

    DOI:10.1088/1674-4926/41/11/111404

    Topics