Fig. 1. Principle of the time-space multiplexed photonic-electronic digital multiplier. (a) Schematic of the proposed multiplier architecture. (b) Logic AND operation realized by two cascading IMs. (c) The generated partial products of 4×4-bit multiplication unfolded in the dimensions of time and space. (d) The summation procedure of the generated partial products. OFC, optical frequency comb; IM, intensity modulator; WDM, wavelength division multiplexer; DBC, decimal to binary converter; CW, continuous wave.

Fig. 2. Experimental results of the 8×2-bit multiplication for 10,011,101×11 at 25 Mbit/s. (a) Experimental setup to realize photonic-electronic digital multiplier. The circles in the diagram represent the waveforms with the same color detected at those points. (b) and (d) Waveforms of generated partial products related to B1 and B2, respectively. (c) Waveform of the mixed signals after WDM. (e) and (f) Waveforms of the DBC’s output ports C1 and C0, respectively. (g) Waveform of the combination between partial products and carry by OC. OC, optical coupler; TDL, tunable delay line; PD, photodetector.

Fig. 3. Experimental results of the photonic-electronic digital multiplier with an input operand of 32 bits. (a) and (b) Multiplication results between a 32-bit binary number A32…A2A1 and a 2-bit binary number 11. (c) Multiplication results between a 32-bit binary number and a 3-bit binary number 101. (d) Multiplication results between a 32-bit binary number and a 4-bit binary number 1001.

Fig. 4. One-step multi-bit DBC realized by the OEO method. (a) Sketch map of multi-bit DBC. (b) The input signal’s state and the corresponding output current level of the PD. (c) Transmission spectrum of the MRR’s drop port under different input signal levels and the input wavelengths.

Fig. 5. Integration scheme of the time-space multiplexed photonic-electronic digital multiplier. (a) Step-by-step summation of the partial products. (b) Schematic diagram of the on-chip photonic-electronic digital multiplier. FPGA, field programmable gate array.