Fig. 1. Electronic system architecture

Fig. 2. Core preamplifier board

Fig. 3. FPGA internal logic

Fig. 4. Trigger fan out board

Fig. 5. Test interface of charge resolution

Fig. 6. Charge resolution of 142 channels

Fig. 7. Test interface of charge integration nonlinearity

Fig. 8. Charge integration nonlinearity of 142 channels

Fig. 9. Test bench

Fig. 10. Position resolution of slit S₃ / S₂ = 0.5/0.3

Fig. 11. Linearity of positions under different slits

Fig. 12. TOF spectra at different slit heights