Design of a high-speed Fast Fourier Transform(FFT) processor is one of key points in a real time signal processing system.In this paper,a high speed and a hybrid architecture FFT processor combining a parallel processing with a Single-Path Delay Feedback(SDF) pipeline is designed based on Field Programmable Gate Array(FPGA) chip. Compared with the full parallel architecture,the memory cost of the designed processor decreases,thus the speed is higher than that of the SDF pipeline architecture. An algorithm and a design model for the processor are established and the three modules in the processor are optimized to decrease the resource cost greatly,thus the speed is higher than that of generous pipeline architectures.a verification is carried out with the FPGA simulations and hardware circuits’ platform in a lab,the results show that the operating frequency reaches 150 MHz and the data flow exceeds 600 Msps.