Oxide semiconductors (OSs), exemplified by indium−gallium−zinc oxide (InGaZnO, IGZO), have demonstrated significant advantages over their silicon counterparts in thin-film transistor (TFT) backplanes for advanced displays^[1−3]. Owing to the relatively high carrier mobility, steep subthreshold swing (SS), low off current, and low-temperature fabrication^[1−5], OSs have also been hotly pursued for various emerging applications beyond displays^[6−13], such as 3D stacking memories^[6−9], compute-in-memory (CIM) chips^{[10, 11]}, and back-end-of-line (BEOL) transistors^{[12, 13]}. A critical requirement for these advanced applications is the downscaling capability of OS transistors.

Among incumbent device architectures of OS transistors, the self-aligned top-gate (SATG) transistor is more promising than bottom-gate (BG) ones, due to the minimized parasitic capacitance and better scaling potential^{[14, 15]}. However, with the channel length (L) decreasing to less than 20 μm, threshold voltage (V_th) roll-off was often observed^[16−20]. Such an apparent "short-channel effect (SCE)" is usually ascribed to the lateral dopant diffusion from source/drain (S/D) to channel, a mechanism known as the "shortening channel effect (CSE)". Previous studies on SCE of SATG OS transistors were mainly performed with a relatively thick gate insulator (GI)^[16−20]. As experienced by silicon MOSFETs^{[21, 22]}, the equivalent oxide thickness (EOT) should also be correspondingly scaled down to sustain an effective gate control.

In this work, the EOT of SATG IGZO transistors was synchronously scaled down to 10 nm along with L decreasing to the sub-micrometer. Unexpectedly, the V_th was observed to roll up first and then off with the continuous shrinking L. While in terms of the V_th evolution, the latter is the so-called "SCE", the former is similar to the reverse short-channel effect (RSCE) in Si MOSFETs^[23−25], which has rarely been reported in IGZO transistors. Both effects could hinder the development of OS transistors towards high integration density applications^{[19, 26]}. Thus, it is of great importance to clarify the origin of V_th roll-up and roll-off in IGZO transistors.

The L-dependence of V_th was comparatively investigated on SATG IGZO transistors with GIs of various thicknesses and different S/D regions. A rivalry between V_th roll-up and roll-off was discovered and is revealed to depend on both GI and S/D. While a thinner GI strengthens the gate control and weakens the V_th roll-off, an insufficiently reduced S/D resistance is clarified to cause the V_th roll-up. Thus, the associative inhibition of both V_th roll-up and roll-off is important for promoting the downscaling capability of OS transistors.

The schematic structure and major processing steps of the SATG IGZO transistors are shown in the inset of Fig. 1. Firstly, 40-nm-thick IGZO was sputtered at room temperature with an argon/oxygen (Ar/O₂) ratio of 47/3 on the glass substrate. The patterned IGZO active islands were treated with the nitrous oxide (N₂O) plasma and in-situ covered with the SiO₂ GI in a plasma-enhanced chemical vapor deposition (PECVD) reactor. A 300 °C annealing was performed in O₂ for 1.5 h to dehydrogenate the SiO₂. After sputtering the molybdenum (Mo) gate electrode, the gate stack (Mo and SiO₂) was patterned together and another 300 °C annealing was performed in O₂ for 0.5 h. Next, a passivation layer (PL) of 200-nm-thick PECVD SiN_x was deposited to form the hydrogenated n⁺-S/D regions. After the final Mo electrodes were contacted with S/D, the electrical characteristics of the resulting transistors were measured using an Agilent B1500 semiconductor parameter analyzer in an ambient atmosphere at room temperature. The electron concentration of the IGZO layer was measured by Hall measurements at room temperature with an Ecopia HMS-3000 Hall Effect Measurement System.

The SATG IGZO transistors with a GI of 10 nm SiO₂ were first characterized. While the channel width (W) is 20 μm, the L varies from 83 to 0.9 μm, with the L shrinking (2ΔL) estimated to be 0.8 μm using the transmission line method (TLM)^[27]. Fig. 2(a) shows the drain current (I_DS) versus gate voltage (V_GS) transfer characteristics measured at a drain voltage (V_DS) of 0.1 V. A noteworthy "SCE" was observed on the sub-micrometer L transistor.

The L-dependences of V_ths measured at V_DSs of 0.1 and 1.0 V were accurately evaluated in Fig. 2(b). The V_th is extracted by the constant-current method from the gate voltage giving a drain current of W/L × 0.1 nA. The standard deviations of the V_th value are consistently below 5%, confirming good device-to-device uniformity. As shown in Fig. 2(b), the V_th exhibits a two-stage evolution. The V_th roll-off from 0.35 to 0.08 V with L decreasing from 4.0 to 0.9 μm is similar to the common "SCE" in OS transistors^[16−18]. Oppositely, during the downscaling of L from 23 to 4.0 μm, the V_th slightly rolls up from 0.24 to 0.35 V. Such V_th roll-up phenomenon is not rare in Si MOSFETs^[23−25], but has not been reported in SATG IGZO transistors. To validate this phenomenon, V_th was also extracted using the linear extrapolation method, which yielded similar trends. The coexistence of V_th roll-up and roll-off further hinders the scaling down of OS transistors towards advanced applications.

In contrast, previous studies on SATG OS transistors with relatively thick GIs observed only V_th roll-off at channel lengths shorter than 20 μm^[16−18]. This suggests that the V_th roll-up effect may have been obscured by the more pronounced V_th roll-off in thicker GI devices. Additionally, it should be noted that variations in W within the micrometer scale have minimal impact on the observed V_th behaviors. To further investigate the origin of the V_th roll-up effect, SATG IGZO transistors with GIs of varying thicknesses were compared.

To reasonably compare the L-dependence of V_th among transistors with different GI thicknesses, the difference (ΔV_th) between V_th of certain L and that of 100 μm-L devices was introduced. Fig. 3(a) shows the L-evolutions of ΔV_th for different SiO₂ thicknesses. For SATG IGZO transistors with 200 nm-thick GI, the V_th directly rolls off for L ≤ 20 μm without roll-up phenomenon, consistent with previous reports^[16−18]. With the GI thinning to 100 nm, an almost negligible‌ V_th roll-up is observed at 10-μm L, tightly followed by the V_th roll-off for L ≤ 6.0 μm. Only for ultrathin 10-nm GI, a significant V_th roll-up cannot be omitted, since the enhanced gate control postpones the V_th roll-off to L ≤ 4.0 μm. These observations suggest a GI-dependent rivalry between V_th roll-up and roll-off during the L downscaling of OS transistors.

As illustrated in the inset of Fig. 3(b), the lateral dopant diffusion causes a ramp profile of carrier concentration (n) from n⁺-S/D to channels^{[16, 17]}. The minimum n in the central channel is thus increased for short-L transistors, resulting in a decreased V_th. Thinner EOT can enhance the gate control over the diffusion-induced n⁻-channel^{[28, 29]}. Thus, the effective V_th roll-off was ameliorated in thinner GI transistors, resulting in a more conspicuous V_th roll-up.

The RSCE in Si MOSFETs features a similar V_th roll-up phenomenon attributed to the increased channel doping concentration near S/D junctions^{[23, 24]}. To investigate the mechanism behind V_th roll-up in IGZO transistors, the channel "doping" concentration and defect density were intentionally adjusted, not through external dopants, but by modifying intrinsic donor-like defects, such as oxygen vacancy (V_o), which are inherent to the material properties of IGZO^[30]. By changing the Ar/O₂ ratio of IGZO sputtering from 47/3 to 48/2, the n increased from 7.5 × 10¹⁶ to 2.4 × 10¹⁷ cm⁻³, as measured by Hall effect measurements, indicating a slightly increased V_o concentration in the inherent channel. The transfer characteristics of these two kinds of IGZO transistors are respectively shown in Figs. 4(a) and 4(b). The latter transistors with higher channel donor concentration exhibit weaker L-dependence. As quantitatively evaluated in Fig. 4(c), the V_th roll-up still exists in the higher "doping" channel, but the degree is suppressed rather than enhanced, suggesting a mechanism different from that in Si MOSFET.

As mentioned, in Si MOSFETs, the roll-up is caused by an increase in channel doping concentration near the S/D regions, which makes it harder to invert the channel. However, in IGZO transistors without a p−n junction, an increase in defect concentration within the channel promotes the accumulation of electrons, facilitating the formation of a conductive channel and V_th roll-off, thus suppressing the V_th roll-up^[30].

To better quantify the influence of defect concentrations in both the channel and the S/D regions on V_th and its scaling behavior, a more detailed analysis is required. An ideal threshold voltage (V_th0) would only depend on the channel, following the classical equation of linear I_DS^[31]:

1IDS=VDSRCH=μeffCOXWL(VGS−Vth0)VDS,

where R_CH, μ_eff, and C_OX are the channel resistance, effective mobility, and GI capacitance. However, during the operation of a practical transistor, the I_DS is determined by not only R_CH but also S/D series resistance (R_SD = R_S+ R_D)^{[32, 33]}, as illustrated in the inset of Fig. 4(d). While R_CH varies with the V_GS and L, R_SD is fixed after device fabrication. The practical V_DS (VSD') and V_GS (VGS') distributed on R_CH are expressed as

2VDS'=RCHRCH+RSDVDS,VGS'=VGS−12RSDRCH+RSDVDS.

The I_DS can be rewritten as

3IDS=μeffCOXWL(VGS−(Vth0+11+(RSDRCH)−1VDS2))×11+RSDRCHVDS,

where the extracted apparent V_th would be larger than V_th0 and increase with the R_SD/R_CH ratio.

Extracted with the TLM, the R_SD/R_CH ratios versus L together with R_SDW values are shown in Fig. 4(d). For SATG IGZO transistors with Ar/O₂ = 47/3, the R_SD/R_CH ratio keeps less than 2% for L > 27 μm but gradually increases to 10% with L reducing to 5.0 μm. This could cause an increase of apparent V_th extracted from I_DS−V_GS curves, consistent with the V_th roll-up for L ≤ 27 μm in Fig. 4(c). For IGZO transistors with Ar/O₂ = 48/2, the added V_o defects enhance the S/D hydrogenation efficiency^{[30, 34]}, considerably decreasing R_SDW from 40.7 to 6.5 Ω∙cm. Therefore, the influence of R_SD/R_CH on V_th becomes weaker, corresponding with an inapparent V_th roll-up in Fig. 4(c). Accordingly, the V_th roll-up behavior is attributed to the gradually increased R_SD/R_CH ratio during the L-downscaling of SATG IGZO transistors.

To evaluate intrinsic gate controllability without the influence of current-induced voltage distribution, the capacitance−voltage (C−V) characteristics were further measured with 10 nm-GI transistors (Fig. 5(a)). As shown in the inset of Fig. 5(b), from the linear extrapolation of the charge-voltage (Q−V) curve^[35], a V_th corresponding to the channel charge accumulation (V_{th_CV}) can be extracted. Without the disturbance of R_SD, the roll-up phenomenon was not observed for the L-dependence of V_{th_CV} in Fig. 5(b). Instead, such gradual V_{th_CV} roll-off is consistent with the lateral n gradient in Fig. 3(b). This confirms the competition between dopant diffusion-induced "SCE" and R_SD-related V_th roll-up.

To further verify the influencing degree of S/D on V_th roll-up and roll-off, BG IGZO transistors were implemented with GI layers of 20 nm SiO₂, as illustrated in the inset of Fig. 6(b). The large S/D-to-BG overlap realized a smaller R_SDW of 5.1 Ω∙cm. As shown in Figs. 6(a) and 6(b), the V_th roll-up phenomenon indeed disappears in the BG transistors, leaving only common "SCE". This further confirms that a sufficiently low R_SD could prevent the V_th roll-up during the synchronous downscaling of L and EOT in OS transistors.

However, because of high parasitic capacitance and large footprint, the BG structure is unsuitable for high-integration applications. Instead, the short-channel SATG OS transistor is highly expected, while the incumbent hydrogen-doped S/D is incompetent. Either the heavy hydrogen doping is accompanied by considerable lateral diffusion^{[16, 17]}, readily causing serious V_th roll-off, or mild hydrogenation cannot form low enough R_SD to prevent V_th roll-up. Recently, several other OS "doping" techniques have been proposed, such as plasma treatment^[36−38], metal reaction^{[27, 39, 40]}, and ion implantation^{[41, 42]}. These methods still struggle with the trade-off between achieving high S/D conductivity and minimizing lateral dopant diffusion, both of which contribute to potential V_th roll-up and roll-off.

Furthermore, the coexistence of V_th roll-up and roll-off poses a significant obstacle to scaling OS transistors in advanced applications. In particular, OS transistors have been explored for capacitor-less (2T0C) DRAM due to their low leakage and process compatibility^{[1, 8, 9]}, but V_th instability remains a key issue impacting memory performance. On one hand, the V_th roll-up can result in insufficient on-state current, which may hinder the write operation speed of DRAM cells^[9]. On the other hand, compared to display applications, high-density circuits typically operate at higher temperatures (up to 125 °C), which could further exacerbate the V_th roll-off in the nanoscale OS transistors and lead to higher leakage currents, reducing the retention time of DRAM cells^{[9, 17, 43, 44]}. Consequently, more advanced S/D metallization techniques, along with jointly optimized processes^{[45, 46]}, are essential for further downscaling SATG OS transistors and addressing these limitations.

Besides the common "SCE" of V_th roll-off, an opposite V_th roll-up with the shrinking L was reported on IGZO transistors with ultrathin GI, where the enhanced gate control weakened the V_th roll-off to manifest the V_th roll-up. The phenomenon of V_th roll-up is quite similar to the RSCE of conventional Si MOSFETs, but a distinct mechanism is clarified to derive from a relatively large R_SD/R_CH ratio. Lower R_SD enabled by either metallic S/D or higher doping would help suppress the V_th roll-up, but the opposite V_th roll-off could deteriorate due to more severe lateral "donor" diffusion from S/D to channel. To downscale the L and GI of OS transistors towards high-integration applications, more advanced S/D engineering is highly expected to jointly eliminate both V_th roll-up and roll-off effects.