Fig. 1. (Color online) TX architecture.

Fig. 2. (Color online) TX FFE and driver architecture.

Fig. 3. (Color online) Timing diagram illustrating FFE tap selection. (a) 1 pre- and 2 post-cursors; (b) 2 pre- and 1 post-cursors.

Fig. 4. (Color online) Clock distribution of TX.

Fig. 5. (Color online) Operation principles of DCC and QEC^[23].

Fig. 6. (Color online) (a) DCC and QEC control cell. (b) Adjustment of duty-cycle and quadrature phase-error.

Fig. 7. (Color online) Half-rate receiver architecture.

Fig. 8. (Color online) Design of the analog front-end. (a) Block diagram; (b) schematic of the CTLE; (c) schematic of the CML buffer with inductive peaking; (d) schematic of the CML buffer with RC source-degeneration.

Fig. 9. (Color online) Frequency responses of CTLE. (a) Peaking gain adjustment; (b) DC adjustment.

Fig. 10. (Color online) Block diagram of half-rate slicer.

Fig. 11. (Color online) (a) Schematic of StrongArm comparator; (b) schematic of proposed reset-and-regenerate comparator; (c) reset mode of proposed comparator; (d) track and regenerate mode of proposed comparator.

Fig. 12. (Color online) Clock-to-Q delay simulation results of (a) strongArm comparator, (b) proposed reset-and-regenerate comparator.

Fig. 13. Schematic of sense-amplifier with S/R latch.

Fig. 14. (Color online) Simulation results of (a) the three-stage comparator, (b) the data slicers.

Fig. 15. (Color online) Block diagram of CDR loop.

Fig. 16. Digital CDR block diagram.

Fig. 17. Schematic of PI.

Fig. 18. (Color online) Simulation results of PI. (a) Simulated output phase versus ideal output phase; (b) INL.

Fig. 19. (Color online) Block diagram of IQ generation.

Fig. 20. (Color online) Simulation results of IQ generation. (a) Transient; (b) phase difference of monte-carlo.

Fig. 21. (Color online) Decoder design. (a) Truth table; (b) schematic.

Fig. 22. (Color online) Chip micrograph.

Fig. 23. (Color online) Measurement setup of (a) RX, (b) TX.

Fig. 24. (Color online) Measured TX Eye diagrams. (a) 28 Gbps NRZ; (b) 56 Gbps PAM-4.

Fig. 25. (Color online) (a) Measured input channel loss; (b) jitter tolerance measurement results.

Fig. 26. (Color online) Measured RX results. (a) Eye diagram of recovered 14 GHz clock; (b) bathtub curve of demultiplexed 875 Mbps data.

Fig. 27. (Color online) Power breakdown. (a) TX; (b) RX.