Microelectronics, Volume. 51, Issue 4, 587(2021)

A New PMTSCR Device with Low Trigger Voltage for Electrostatic Discharge Protection

LIAO Changjun1, HUANG Qiupei2, HE Minghao2, WANG Xin2, ZHENG Tongwen2, and LIU Jizhi2
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
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    References(12)

    [1] [1] WU J, JULIANO P, ROSENBAUM E. Breakdown and latent damage of ultra-thin gate oxides under ESD stress conditions [C] // Proc EOS/ESD Symp. Anaheim, CA, USA. 2000: 287-295.

    [2] [2] ALTOLAGUIRRE F A, KER M D. Area-efficient ESD clamp circuit with a capacitance-boosting technique to minimize standby leakage current [J]. IEEE Trans Dev Mater Reliab, 2015, 15(2): 156-162.

    [3] [3] KER M D, HSU K C. Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits [J]. IEEE Trans Dev Mater Reliab, 2005, 5(2): 235-249.

    [4] [4] SHAN Y, HE J, HU B, et al. NLDD/PHALO-assisted low-trigger SCR for high-voltage-tolerant ESD protection without using extra masks [J]. IEEE Elec Dev Lett, 2009, 30(7): 778-780.

    [5] [5] WATT J T, WALKER A J. A hot-carrier triggered SCR for smart power bus ESD protection [C] // Proc IEDM. Washington D C, USA. 1995: 341-344.

    [6] [6] RUSS C, MERGENS M P J, ARMER J, et al. GGSCR: GGNMOS triggered silicon controlled rectifiers for ESD protection in deep submicron CMOS processes [C] // Proc EOS/ESD Symp. Anaheim, CA, USA. 2001: 22-31.

    [7] [7] JANG S L, GAU M S, LIN J K. Novel diode-chain triggering SCR circuits for ESD protection [J]. Sol Sta Elec, 2000, 44(7): 1297-1303.

    [8] [8] LIN C Y, WU Y H, KER M D, Low-leakage and low-trigger-voltage SCR device for ESD protection in 28-nm high-k metal gate CMOS process [J]. IEEE Elec Dev Lett, 2016, 37(11): 1387-1390.

    [9] [9] CHATTERJEE A, POLGREEN T. A low-voltage triggering SCR for on-chip ESD protection at output and input pads [J]. IEEE Elec Dev Lett, 1991, 12(1): 21-22.

    [11] [11] LINC, CHEN C. Resistor-trigger SCR device for ESD protection in high-speed I/O interface circuits [J]. IEEE Elec Dev Lett, 2017, 38(6): 712-715.

    [12] [12] DU F B, SONG W Q, HOU F,et al. Augmented DTSCR with fast turn-on speed for nanoscale ESD protection applications [J]. IEEE Trans Elec Dev, 2020, 67(3): 1353-1356.

    [13] [13] CHENJ, LIN C, KER M. On-chip ESD protection device for high-speed I/O applications in CMOS technology [J]. IEEE Trans Elec Dev, 2017, 64(10): 3979-3985.

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    LIAO Changjun, HUANG Qiupei, HE Minghao, WANG Xin, ZHENG Tongwen, LIU Jizhi. A New PMTSCR Device with Low Trigger Voltage for Electrostatic Discharge Protection[J]. Microelectronics, 2021, 51(4): 587

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    Paper Information

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    Received: Nov. 24, 2020

    Accepted: --

    Published Online: Feb. 21, 2022

    The Author Email:

    DOI:10.13911/j.cnki.1004-3365.200542

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