NAND flash memory is widely used for data storage due to its high storage density, high throughput, and low power consumption. The three-dimensional (3D) NAND flash and multi-level cell data coding techniques provide higher density and lower cost per bit, but at the expense of storage reliability. NAND controller companies have been employing stronger error-correction-codes (ECC) such as BCH and LDPC codes to correct the data errors in NAND flash. But when error number exceeds ECC’s correction capability, the data errors cannot be corrected by ECC. Therefore, several NAND flash error mitigation techniques have been proposed in previous works as supplementary schemes of ECC. In this paper, an introduction of NAND flash memory basics and error patterns was presented, and a review of state-of-the-art error mitigation techniques was given, which provided a useful reference for designing a more reliable storage system.