Fig. 1. Schematic diagram of the CMOS inverter

Fig. 2. The TAT effect in the oxide layer

Fig. 3. Schematic of the fast-rising-edge EMP resulting voltage signal experiment based on the TLP testing system

Fig. 4. Injection experiments of EMP resulting voltage signal with fast rising edges

Fig. 5. Typical TLP current-voltage characteristic curve and reverse leakage current curve of type A sample

Fig. 6. Tested output level of the CMOS inverter

Fig. 7. Simulation results of the CMOS device under EMP resulting voltage signal

Fig. 8. Simulated current density under EMP resulting voltage signal. Detailed current distribution of the NMOS region under (a) 0 V, (c) 5 kV, and (e) 10 kV. The corresponding current of the PMOS region is shown in (b), (d) and (f)

Fig. 9. Lattice temperature of the CMOS inverters under EMP resulting voltage signal

Fig. 10. Peak temperature of the CMOS inverter under EMP resulting interference with (a) 1 kV and (b) 10 kV amplitudes and 0.2 ns to 2 ns rising edges